一种基于总剂量效应的SOI器件模型快速提取方法

从工程应用的角度介绍了一种基于总剂量效应的SOI器件模型参数的快速提取方法。首先,提取0 krad(Si)时器件的模型参数,然后针对总剂量敏感参数,对100 krad(Si)总辐射试验后的同种器件进行模型参数优化,并对得到的模型参数进行验证。结果表明,该方法所提取的模型参数准确有效,解决了国内目前在抗辐照SOI工艺中因采用标准SOI工艺SPICE模型(如BSIMSOI等)导致不能反映辐照效应对器件特性的影响且无法给出经过不同辐照剂量之后的器件特性的缺点,可用于评估辐射对SOI电路的影响。     

深亚微米全耗尽SOI MOSFET参数提取方法的研究

基于BSIMSOI对深亚微米全耗尽SOI MOSFET参数提取方法进行了研究,提出一种借助ISE器件模拟软件进行参数提取的方法。该方法计算量小,参数提取效率高,不需要进行繁琐的器件数学建模,易于推广。将该方法提出的模型参数代入HSPICE进行仿真,模拟结果与实验数据相吻合,证明了这种方法的有效性和实用性。     

基于遗传算法的BSIM SOI模型参数提取

提出了一种提取BSIM SOI模型参数的新方法,该方法基于遗传算法和局部优化法的结合,同时具有全局优化和局部优化的优点,提取的参数物理意义明确,并且容易得到全局最优解.该方法计算简单,不需要对模型进行深入了解和丰富的参数提取经验,易于推广使用.对用该方法得到的SOI模型进行了模拟,并将模拟结果与1.2μm CMOS/SOI测试结果进行对比,二者吻合很好,SOI器件特有的kink效应也得到了很好的拟合.     

基于遗传算法的BSIM SOI模型参数提取

提出了一种提取BSIM SOI模型参数的新方法,该方法基于遗传算法和局部优化法的结合,同时具有全局优化和局部优化的优点,提取的参数物理意义明确,并且容易得到全局最优解．该方法计算简单,不需要对模型进行深入了解和丰富的参数提取经验,易于推广使用．对用该方法得到的SOI模型进行了模拟,并将模拟结果与1.2μm CMOS/SOI测试结果进行对比,二者吻合很好,SOI器件特有的kink效应也得到了很好的拟合．     

基于MPI的全局并行遗传算法的SOI MOS器件模型参数提取

提出了将全局并行遗传算法应用于模型参数提取,并应用于标准的1.2μm CMOS/SOI工艺的SOI MOSFET器件,一次性提取BSIMSOI3模型主要的42个直流参数.实验结果表明,该方法不依赖参数初始值、精度高、效率高,降低了SOI模型参数提取工作的难度,具有很强的通用性,易于移植优化及数据拟合.     

基于混合遗传算法的SOI MOSFET模型参数提取

通过将遗传算法和模拟退火算法相结合得到了改进的遗传算法,这种改进的遗传算法可用于提取SOI MOSFET模型参数.用这种方法提取了基于中国科学院微电子研究所开发的标准的1.2μm CMOS/SOI工艺的SOI MOSFET模型参数,用此模型模拟的数据与测试数据吻合很好,与商业软件相比精度得到了明显的提高.这种方法与商业软件使用的传统的方法相比,不需要对SOI MOSFET模型有非常深入的了解,也不需要复杂的计算.更深入的验证表明,该模型适用的器件尺寸范围很广.     

0.35μm SOI CMOS器件建模技术研究

介绍了SOI技术的优势和器件建模的意义.针对0.35μmSOI CMOS工艺的开发,设计了用于建模的测试芯片.对于SOIMOSFET中存在的自加热等寄生效应设计了参数提取的流程,并设计了相应的测试方法.在得到所需的测试数据后,采用局部优化方法进行参数提取.最后通过模型仿真结果和测试数据的比较证明了建立的0.35μm SOI CMOS模型有较高的精度.     

基于混合遗传算法的SOI MOSFET模型参数提取

通过将遗传算法和模拟退火算法相结合得到了改进的遗传算法,这种改进的遗传算法可用于提取SOI MOSFET模型参数.用这种方法提取了基于中国科学院微电子研究所开发的标准的1.2μm CMOS/SOI工艺的SOI MOSFET模型参数,用此模型模拟的数据与测试数据吻合很好,与商业软件相比精度得到了明显的提高.这种方法与商业软件使用的传统的方法相比,不需要对SOI MOSFET模型有非常深入的了解,也不需要复杂的计算.更深入的验证表明,该模型适用的器件尺寸范围很广.     

一种新型的基于SOI MOSFET 衬底模型提取方法

衬底寄生网络建模和参数提取,对RF SOI MOSFET器件输出特性的模拟有着非常重要的影响。考虑BOX层引入的体区和Si衬底隔离,将源、体和衬底短接接地,测试栅、漏二端口S参数的传统测试结构,无法准确区分衬底网络影响。文章提出一种改进的测试结构,通过把SOI MOSFET的漏和源短接为信号输出端、栅为信号输入端,测试栅、漏/源短接二端口S参数的方法,把衬底寄生在二端口S参数中直接体现出来,并开发出一种解析提取衬底网络模型参数的方法,支持SOI MOSFET衬底网络模型的精确建立。采用该方法对一组不同栅指数目的SOI MOSFET进行建模,测量和模型仿真所得S参数在20GHz频段范围内得到很好吻合。     

一种改进的用于SiGe HBT的焊盘模型参数提取技术

提出了一种适用于Si基器件的焊盘寄生参数的提取方法,并将此方法提取的焊盘寄生参数结果与用近似法提取的焊盘寄生参数结果的精度作了比较。比较结果表明,文中提出的线性拟合法精度较高。焊盘寄生参数提取并剥离后,对AMS 0.35μm BiCMOS工艺加工的SiGe HBT的小信号等效电路进行参数提取,其中,外部电阻用基极"过驱动电流"法提取,本征参数用分析法提取,将参数提取结果代入模型进行仿真,仿真得到的S参数在整个测试频率范围内均与测试结果吻合良好。     

Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET

This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20-nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters.     

Deep submicron PDSOI thermal resistance extraction

Deep submicron partially depleted silicon on insulator (PDSOI) MOSFETs with H-gate were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences. Because the self-heating effect (SHE) has a great influence on SOI, extractions of thermal resistance were done for accurate circuit simulation by using the body-source diode as a thermometer. The results show that the thermal resistance in an SOI NMOSFET is lower than that in an SOI PMOSFET; and the thermal resistance in an SOI NMOSFET with a long channel is lower than that with a short channel. This offers a great help to SHE modeling and parameter extraction.     

Technology and electric characteristics of the field-effect hall sensor based on SOI structure

Dependences of electric characteristics on the technological parameters of the field-effect Hall sensors based on SOI structures (FEHS-SOI) are discussed. The manufacturing process for the formation of a magnetosensitive structure comprising the field-effect Hall sensor based on a MOSFET in the SOI structures was simulated. Electrical characteristics of the device were calculated and the optimization research devoted to the influence of process parameters on the FEHS-SOI voltage-current characteristics and sensitivity was made.     

Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz.     

Analysis of floating body induced transient behaviors in partiallydepleted thin film SOI devices

Emphasis toward manufacturability of thin film SOI devices has prompted more attention on partially depleted devices. In this paper, drain current transients in partially depleted SOI devices due to floating-body effects are investigated quantitatively. A one-dimensional analytical model is developed to predict the transient effect and MEDICI simulation is performed to confirm the model. With the model, the amount of the turn-on current enhancement and the turn-off current suppression are calculated. The transient characteristics can be used in investigating the quality of the SOI materials by determining the carrier lifetime. The impact of the transient effect on the device parameter extraction is described     

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

In this paper, a new compact charge based DC model for the drain current of long channel fully depleted ultra-thin body SOI MOSFETs and asymmetric double-gate MOSFETs with independent gate operation (ADGMOSFETs) is presented. The model was validated by both TCAD simulations and electrical measurements with a good agreement. In particular, great care was taken during the derivation of the model in order to respect the physics of the device and to make the correct approximations. The obtained solutions can be viewed as a generalization of classical MOS theory to the case of undoped fully depleted ADGMOS. As a result, the model consists of relatively simple equations and is a promising approach for the compact modeling and parameter extraction of fully depleted SOI transistors.     

Measurement and modeling of self-heating in SOI nMOSFET's

Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries     

质子引入的6T SRAM单粒子翻转截面预测模型

提出了一种基于SOI工艺6T SRAM单元质子辐射的单粒子饱和翻转截面的预测模型,该模型通过器件物理来模拟辐照效应,利用版图和工艺参数来预测质子引入的单粒子饱和翻转截面。该模型采用重离子的SPICE测试程序对质子辐射的翻转截面进行预测,该方法简单高效,测试实例表明在0.15μm SOI工艺下,预测的质子引入的单粒子翻转饱和截面和实际测试的翻转截面一致。     

Determination and assessment of the floating-body voltage of SOICMOS devices

A self-consistent method to extract the off-state floating-body (FB) voltage of SOI CMOS devices is presented. The technique is simple and is based on CV and S-parameter measurements of a single standard SOI MOSFET device; no special test structure design is needed. The bias dependent S-parameter measurements of the FB SOI device and its equivalent circuit, along with the CV measurements between the drain and source of the same device, are used to determine the FB voltage. The technique provides reasonable insight on device off-state and leakage performances that are important for digital applications. Additionally, it proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depleted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage, demonstrating the importance of understanding FB effects on device off-state and junction leakage performances     

A new parameter extraction technique for small-signal equivalentcircuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz