DC analysis of current mode logic

A closed-form solution to finding the optimum signal swing for CML (current-mode logic) is illustrated, based on a few parameters of the minimum geometry transistor in a given technology. A simplified transistor model is used to develop the concept of noise margin optimized for both transistor and circuit parameters. It is shown that the voltage swing of the CML gate is not an arbitrary choice for the circuit designer but is deterministic. The effects of gate fan-in and series gating are then included as part of the closed-form solution, yielding an optimized set of parameters for defining all logic functions. Calculation of the maximum fan-out as well as bias regulators and calculation of the voltage drops in the power buses of chip layouts are treated. The procedure described has been used to develop a CML cell library for producing high-performance interface and networking circuits     

Low-power tri-state buffer in MOS current mode logic

In this paper, a low-power tri-state buffer in MOS current mode logic (MCML) is proposed. It offers power saving by reducing the overall current flow in the circuit during the high-impedance state. The proposed MCML tri-state buffer is simulated in PSPICE using 0.18 μm TSMC CMOS technology parameters. Its performance comparison with the existing MCML tri-state buffers indicates that the proposed tri-state buffer is power efficient than the others.     

Design of ultra low power current mode logic gates using magnetic cells

Non-volatile logic is a viable solution to overcome the leakage power issue which has become a major obstacle to CMOS technology scaling. Magnetic tunnel junction (MTJ)-based logic is a promising approach because of the non-volatility, less occupied area, almost zero static power consumption, programmability. This paper presents current mode logic gates using MTJ elements without any intermediate electronic circuitry. This efficient solution reduces the performance overheads of the spintronic logic circuits while simplifying fabrication. Hspice based simulations have been carried out to verify the performance of different logic gates. The simulation results reveal that the SBEG based gates provide less area, power consumption, and energy while also offering less design complexity as compared to mLogic (previously proposed magnetic logic) and CMOS gates.     

Self-aligned GaAs p-channel enhancement mode MOS heterostructurefield-effect transistor

Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga₂O₃ gate oxide, an undoped Al_0.75Ga_0.25As spacer layer, and undoped In_0.2Ga_0.8As as channel layer. The p-channel devices with a gate length of 0.6 μm exhibit a maximum DC transconductance g_m of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality     

High-speed low-power logic ICs using quasi-normally-off GaAs MESFETs

A digital approach, called `low pinchoff-voltage FET logic' (LPFL), is proposed for high-speed LSI circuit applications. It makes use of `quasi-normally-off' GaAs MESFETs, i.e., Schottky-gate devices operating in enhancement model with a pinchoff-voltage ranging between -0.2 and +0.2 V. Such a V/SUB P/ range is about twice that tolerated by conventional normally-off circuits and thus higher fabrication yields can be routinely achieved. Performances which can be achieved with this approach have been tested by means of a single-clocked frequency divider circuit fabricated with MESFETs of 1 /spl mu/m/spl times/20 /spl mu/m gate geometry.     

Zero gate leakage current in the enhancement mode MOSFET

Gate leakage current measurements of the enhancement mode MOSFET taken with a vibrating reed electrometer in a carefully controlled environment indicate that zero gate leakage current can be achieved. The zero region is delineated by the change of sign in the gate leakage current when the drain-to-source voltage is increased.     

Metamorphic InAlAs/InGaAs enhancement mode HEMTs on GaAs substrates

In_0.5Al_0.5As/In_0.5Ga_0.5 As HEMTs have been grown metamorphically on GaAs substrates oriented 6° off (100) toward (111)A using a graded InAlAs buffer. The devices are enhancement mode and show good dc and RF performance. The 0.6-μm gate length devices have saturation currents of 262 mA/mm at a gate bias of 0.7 V and a peak transconductance of 647 mS/mm. The 0.6 μm×3 mm devices tested on-wafer have output powers up to 30 mW/mm and 46% power-added-efficiency (PAE) at 1 V drain bias and 850 MHz. When biased and matched for best efficiency performance, this same device has up to 68% PAE at V_d=1 V     

Analysis and design of CMOS fuzzy logic controller in current mode

This paper presents a new definition of fuzzy numbers. Employing the new definition, the new approach to the design of a current mode fuzzy microchip controller was performed. The controller was constructed with CMOS current mirrors. The circuit allowed two premises, one conclusion, and nine rules; the latter were programmable with current sources. The chip consumed 2 mA at a 5 V power supply for a core area of 0.4 mm². Furthermore, the performance of the developed fuzzy architecture reached 10 M FLIPS (fuzzy inferences per second) for the standard 1.2 μm CMOS technology. We present a real-time application that successfully used the chip to control a metallic ball with an electromagnetic field. Finally, we discuss the silicon compiler, called SCOFIC, used for the automatic synthesis of the above circuit     

A high speed GaAs 8-bit multiplexer using capacitor-coupled logic

Capacitor-coupled logic has been used to design and fabricate a GaAs eight channel multiplexer IC for use at 1.2 Gbit/s, which is fully compatible with ECL, and which offers good stability and very high tolerances to device parameters and circuit voltages. A technique has been developed to enable initial charging of all the coupling capacitors, upon application of a simple pulse sequence to control lines. Preliminary results show correct operation of the multiplexer when operated on wafer probes up to 250 MHz, the present practical limit for such measurements. Higher frequency measurements will be carried out on packaged devices, but these results are not yet available. The divide-by-two elements in the multiplexer can be programmed to self oscillate at /SUP 1///SUB 4/ their maximum usable frequency, allowing simple testing of high frequency performance. A very good agreement between the measured maximum usable frequencies and those predicted from the oscillation frequencies has been achieved, with over 60 percent yield for dividers. On the basis of these preliminary results, indicating operation at speeds up to about 600 MHz, it is anticipated that future wafers with 1 /spl mu/m gate lengths will operate at 1.2 Gbits/s.     

Delay components of a current mode logic circuit and their currentdependency

The delay of a CML circuit can be described in terms of the delay elements of a bipolar transistor such as junction capacitors C_BC , C_BE, C_CSand a cutoff frequency f_T . A new analysis method is proposed to calculate a CML delay. The nonlinear conductance of a bipolar transistor is approximated by a piecewise linear function. A resistor network is then picked up from the CML equivalent circuit to characterize the dc operation. This resistor network and the delay elements determine the CML delay. Subcircuits containing the resistor network and one or two of the delay elements of C_BC, C^BE, C_CS, and f_T are separately analyzed to clarify the delay components. The total CML delay is estimated from a linear sum of the delay components for a step input response. Current dependency of the CML delay Is also discussed     

GaAs enhancement mode FET-tunnel diode ultra-fast low power inverter and memory cell

A microtunnel diode load for a normally off enhancement mode gallium arsenide field effect transistor provides a compact inverter circuit of fast switching speed and low power consumption. Level shifting is not required, and direct coupling with multiple fan-out causes a comparatively small decrease in speed. The tunnel diode FET logic (TDFL) should be capable of operation at 2 GHz with a power-delay time product of 3.4 fJ for an output node capacitance of 50 fF. The negative characteristic of the tunnel diode combined with the FET provides a compact memory cell. However, advances in the state of the art for producing microtunnel diodes of precisely controlled peak current will be required before a viable TDFL can emerge.     

Experimental observation of velocity overshoot in n-channelAlGaAs/InGaAs/GaAs enhancement mode MODFETs

Velocity overshoot phenomena in n-channel Al-GaAs/InGaAs/GaAs enhancement mode MODFETs have been investigated for gate lengths ranging from 1 to 0.5 μm. The study is based on Motorola's established CGaAs ^TM technology. The observed average electron velocity υ _aυ under the gate is 1.05, 1.34, 1.48, and 1.71×10 ⁷ cm/s for a gate length L_G of 1, 0.7, 0.6, and 0.5 μm, respectively. The presence of velocity overshoot in InGaAs channels is clearly proven with average electron velocities exceeding the steady-state saturation velocity of ≅1×10⁷ cm/s for L_G⩽0.7 μm, and with the significant increase of υ_aυ with shorter gate length     

Precise realisation of current mode integrator using current conveyor

The realisation of a differential input current mode integrator network using the second generation current conveyor (CC II) is proposed. Even with nonideal CC IIs, true differential input capability and precise compensation of the time constant tau can be obtained by suitable design. A minimum of passive RC components is needed; their interchanged connection yields alternate differentiator functions.<>     

Planar GaAs MOSFET integrated logic

Selective and multiple ion implantations directly into a semi-insulating GaAs substrate were utilized to fabricate planar integrated circuits with deep-depletion plasma-grown native oxide gate GaAs MOSFET's. 1.2-µm gate 27-stage enhancement/depletion (E/D) type ring oscillators, with the circuit optimized to reduce parasitic capacitance, were fabricated (using conventional photolithography) to assess the speed-power performance in digital applications. A minimum propagation delay of 72 ps with a power-delay product of 139 fJ was obtained, making these devices the fastest among current GaAs and Si logic fabricated by conventional photolithography. A minimum power-delay product of 36 fJ with a propagation delay of 157 ps was obtained. The power-delay product is comparable with that of 1.2-µm gate GaAs E-MESFET logic, and the speed is more than twice as great. This paper includes a comparison of the theoretical cut off frequency of MESFET and MOSFET logic devices operating in depletion mode. Results indicate that MOSFET logic has superior potential for high-speed operation.     

GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 μm non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps     

An improved current mode logic latch for high‐speed applications

In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.     

An all implanted self-aligned enhancement mode n-JFET with Zn gatesfor GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p⁺ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 μm JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p⁺/n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f_t of 19 GHz with an f_max of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits     

GaAs trickle transistor dynamic logic

A GaAs dynamic logic gate is proposed which uses a trickle transistor to compensate for leakage from the precharged node. This trickle transistor dynamic logic (TTDL) circuit is configured as a domino logic gate and a differential cascode voltage switch logic (CVSL) gate. Delay chains were implemented in a 1-μm GaAs enhancement/depletion (E/D) process where the depletion-mode FETs (DFETs) and the enhancement-mode FETs (EFETs) have threshold voltages of -0.6 and 0.15 V, respectively, in order to obtain an experimental characterization of these gates. In addition, the TTDL gates were used to implement a 4-b carry-lookahead adder. The adder has a critical delay of 0.8 ns and a power dissipation of 130 mW