共查询到20条相似文献,搜索用时 109 毫秒
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SOI器件具有高速、低压、低功耗、抗辐照、耐高温等体硅器件不具备的优点,SOI CMOS技术开始用于深亚微米高速、低功耗、低电压大规模集成电路应用。但SOI技术还面临浮体效应、自加热效应等问题的挑战。作为SOI模型国际标准,BSIM3SOIv1.3提出了新的模型参数解决方案。BSIMPDSPICE器件模型是基于物理意义的模型,是在体硅MOS器件模型工业标准(BSIM3V3)的基础上开发而成,BSIMPD针对SOI固有的浮体效应引起的动态特性,自加热和体接触提出相应的模型参数。 相似文献
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研究开发了0.4 μm PD CMOS/SOI工艺,试制出采用H栅双边体引出的专用电路.对应用中如何克服PD SOI MOSFET器件的浮体效应进行了研究;探讨在抑制浮体效应的同时减少对芯片面积影响的途径,对H栅双边体引出改为单边体引出进行了实验研究.对沟道长度为0.4 μm、0.5 μm、0.6 μm、0.8 μm的H栅PD SOI MOSFET单边体引出器件进行工艺加工及测试,总结出在现有工艺下适合单边体引出方式的MOSFET器件尺寸,并对引起短沟道PMOSFET漏电的因素进行了分析,提出了改善方法;对提高PD CMOS/SOI集成电路的设计密度和改进制造工艺具有一定的指导意义. 相似文献
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薄膜全耗尽SOI CMOS电路高温特性模拟和结构优化 总被引:1,自引:1,他引:0
在300~600K温度范围内,利用ISE TCAD模拟软件对全耗尽SOI电路的温度特性进行了模拟分析,得到了较全面的SOI CMOS倒相器静态特性和瞬态特性,并提出了一种改进的AlN-DSOI结构.结果显示,SOI CMOS电路的阈值电压对温度较为敏感,随着温度的升高,输出特性衰退明显.瞬态模拟也表明电路的速度和功耗受外界环境温度的影响较大.改进后的AlN-DSOI结构在有效缓解SOI结构热效应和浮体效应的基础上,显著提高了电路的速度和驱动能力. 相似文献
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薄膜SOI/CMOS的SPICE电路模拟 总被引:1,自引:0,他引:1
鉴于SPICE是目前世界上广泛采用的通用电路模拟程序,具具有可扩展模型的灵活性,我们通过修改SPICE源程序把新器件模型--SOIMOSFET模型移植入SPICE中,通过我们的模拟工作,证实了我们模型的正确性和电路实用性,分析了器件参数对SOI/CMOS电路速率的影响,这些结论可以很好地指导电路设计和工艺实践。 相似文献
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Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits
D. Flandre J. P. Colinge J. Chen D. De Ceuster J. P. Eggermont L. Ferreira B. Gentinne P. G. A. Jespers A. Viviani R. Gillon J. P. Raskin A. Vander Vorst D. Vanhoenacker-Janvier F. Silveira 《Analog Integrated Circuits and Signal Processing》1999,21(3):213-228
This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis. 相似文献
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Mansun Chan Bin Yu Zhi-Jian Ma Nguyen C.T. Chenming Hu Ko P.K. 《Electron Devices, IEEE Transactions on》1995,42(11):1975-1981
This paper compared the performance of conventional fully depleted (FD) SOI MOSFETs and body-grounded nonfully depleted (NFD) SOI MOSFETs for analog applications, A new low-barrier body-contact (LBBC) technology has been developed to provide effective body contact. Experimental results show that the NFD MOSFET's with LBBC structure give one order of magnitude higher output resistance, significantly lower flicker noise, improved subthreshold characteristics, and minimal threshold voltage variation compared with conventional FD SOI MOSFETs. The device characteristics of the LBBC MOSFET's are more desirable for fabricating high performance analog or mixed analog/digital CMOS circuits 相似文献
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采用CoSi2 SALICIDE结构CMOS/SOI器件辐照特性的实验研究 总被引:2,自引:0,他引:2
讨论了CoSi2SALICIDE结构对CMOS/SOI器件和电路抗γ射线总剂量辐照特性的影响。通过与多晶硅栅器件对比进行的大量辐照实验表明,CoSi2SALICIDE结构不仅可以降低CMOS/SOI电路的源漏寄生串联电阻和局域互连电阻,而且对SOI器件的抗辐照特性也有明显的改进作用。 相似文献
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采用SIMOX材料,研制了一种全耗尽CMOS/SOI模拟开关电路,研究了全耗尽SOI MOS场效应晶体管的阈值电压与背栅偏置的依赖关系,对漏源击穿的Snapback特性进行分析,介绍了薄层CMOS/SIMOX制作工艺,给出了全耗尽CMOS/SOI电路的测试结果。 相似文献
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Stasiak D.L. Mounes-Toussi F. Storino S.N. 《Solid-State Circuits, IEEE Journal of》2001,36(10):1546-1552
A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits 相似文献
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The design, operation, and characterization of CMOS imagers implemented using: 1) "regular" CMOS wafers with a 0.5-mum CMOS analog process; 2) "regular" CMOS wafers with a 0.35-mum CMOS analog process; and 3) silicon-on-insulator (SOI) wafers in conjunction with a 0.35-mum CMOS analog process, are discussed in this paper. The performances of the studied imagers are compared in terms of quantum efficiency, dark current, and optical bandwidth. It is found that there is strong dependence of quantum efficiency of the photodiodes on the architecture of the image sensor. The results of this paper are useful for designing and modeling CMOS/SOI image sensors 相似文献
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Kerns S.E. Shafer B.D. Rockett L.R. Jr. Pridmore J.S. Berndt D.F. van Vonno N. Barber F.E. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1988,76(11):1470-1509
Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ICs 相似文献