The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

Thermal and stress analysis of semiconductor wafers in a rapidthermal processing oven

Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed     

Thermal uniformity of 12-in silicon wafer during rapid thermalprocessing by inverse heat transfer method

Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated     

The Effect of Thermal Shocks on the Stresses in a Sapphire Wafer

Sapphire wafers can experience temperature variations during processing in a furnace, which in turn can cause large deformation and stresses in the wafers. This paper aims to reveal the mechanism of stress development and evolution in sapphire wafers during thermal shocks, as well as the dependence of the stresses on some process parameters. Finite-element stress analysis was conducted on a single sapphire wafer subjected to thermal shocks. The results show that the thermal gradient in the radial direction induces high stresses even in mechanically unrestrained wafers. The largest stress components occur at the wafer edge as the largest normal stresses are circumferential; whereas the maximum tensile stress is realized upon cooling, the highest value of the maximum shear stress and the minimum compressive stress eventuate in the heating-up phase. The normal stresses have a parabolic distribution in the radial direction. It was found that holding the furnace temperature leads to a more uniform temperature distribution across the wafer but brings about higher tensile stresses in the cooling phase     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Transient effects in rapid thermal processing

Using a realistic model of a rapid thermal processing chamber including Navier-Stokes calculations of the gas losses, the stresses and yield strengths of silicon wafers were determined for several linear ramp rates. It was found that the stress to yield strength ratio is a sensitive function of the ramp rate and the radiant uniformity. Radiation patterns that produce good steady-state thermal nonuniformity overheat the wafer edges during heating transients, leading to high stress levels     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

快速热处理对PECVD氮化硅薄膜性能的影响

利用PECVD在硅片上沉积了氮化硅(SiNx)薄膜,将沉积膜后的样品放在N2气氛中进行快速热处理(RTP),研究了不同快速热处理对PECVD氮化硅薄膜件能的影响.采用原子力显微镜(AFM)检测薄膜的表面形貌,利用椭圆偏振仪测量样品膜厚和折射率,利用准稳态光电导衰减法(QSSPCD)测鼋样品的少子寿命.实验结果表明随着RTP温度的升高,薄膜厚度迅速减小,折射率迅速增大;低于500℃热处理时,少子寿命基本不变;高于500℃热处理时,随着温度的升高,少子寿命急剧下降.氮化硅薄膜经热处理后反射率基本不变.     

Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

Full Field Temperature Measurement of Specular Wafers During Rapid Thermal Processing

Many of the processes involved in the creation of semiconductor devices involve high-temperature processing of silicon wafers. The benefits of reduced thermal budget and faster cycle time make rapid thermal processing (RTP) a possible key technology for semiconductor manufacturing. However, the problem of nonuniform wafer temperature has prevented it from further spread among the industry. The first step in developing controls to maintain a uniform wafer temperature is accurate temperature measurement during processing. In this paper, a system was developed to exploit the specular reflectivity of silicon wafers and obtain a measurement of the wafer temperature profile. The spectral reflectivity is determined by measuring the intensity of an incident beam and the beam reflected from the wafer surface. With this measured reflectivity value the spectral-directional wafer emissivity was determined using Kirchhoff's law. The obtained emissivity then was used to calculate the wafer temperature profile from an image obtained with an infrared camera. An experimental study of the transmittance of an undoped silicon calibration wafer at an elevated temperature is also discussed     

Transient thermal behavior in a new RTP chamber

The transient thermal behavior of 200 and 300 mm wafers in a new rapid thermal processing (RTP) chamber is investigated. The AST3000 is a new RTP tool to meet the process requirements for both wafer sizes in 0.18 μm technologies and beyond. In this paper, experimental results obtained on both 200 and 300 mm wafers for varying processing conditions are shown: spike anneal experiments with fast ramp rates up to 200°C/s were performed. For standard anneal recipes, the steady state time is varied in a broad range and also the inherent temperature uniformity is investigated.     

The parylene-aluminum multilayer interconnection system for wafer scale integration and wafer scale hybrid packaging

Polyimides have been considered as interlayer dielectrics for wafer scale integration (WSI) and wafer scale hybrid packaging (WSHP). However, high temperature curing steps for polyimide lead to large stresses in polyimide films. This is due to differing thermal expansion coefficients of the metal conductor, insulator and substrate materials causing yield and reliability problems. Polyimides also require the use of solvents, and tend to outgas during subsequent processing. They tend to absorb moisture with resulting degradation of dielectric constants. Also, the spin on method used to apply and planarize polyimide layers exhibits nonuniformity of thickness on large wafers. In this paper we examine parylene (Poly-p-xylylene) and some of its derivatives as possible interlayer dielectrics due to some of their attractive features. Parylene has a low dielectric constant. It can be vapor deposited at low temperatures and in vacuum. It is also highly resistant to corrosion and is a clear, transparent material with possible use for optical interconnections. This paper studies the reactive ion etching properties for polyimides and parylenes in an oxygen containing plasma under identical conditions. The etching rates of the parylenes and polyimides have been compared. The surface properties of these polymers are examined. Further, the film growth properties of aluminum deposited on the etched surfaces using the ionized cluster beam are investigated.     

Improvement in ultrathin rapid thermal oxide uniformity by thecontrol of gas flow

A methodology to improve the temperature uniformity for the wafer in a rapid thermal processing (RTP) system is presented. The work aims at the temperature compensation at the wafer surface by thermal convection. From simulation results of the flow field, it is seen that the cold gas, while flowing from the periphery of the wafer toward the wafer center, causes a lower pressure at and around the center. This lower pressure is due to the flow away of gas by buoyancy and it aggregates thermal nonuniformity. A technique is suggested that consists of suppressing the upward gas flow using a transparent quartz cap above the monitored wafer. Simulation and experimental results show that by implementing this technique, the temperature uniformity of the wafer is improved     

Rapid thermal processing uniformity using multivariable control ofa circularly symmetric 3 zone lamp

Defect introduction and process variations commonly observed in conventional rapid thermal processing (RTP) systems have impeded its widespread acceptance in manufacturing. The main problem lies in the conventional approach of using scalar control, where optimal steady-state temperature uniformity at one set of processing conditions is used to fix the hardware geometry, leaving only one input variable-the lamp power-for control. It is demonstrated that this control is inadequate, since the radiative and convective heat exchange at the wafer are functions of the processing conditions, and that the resultant nonuniformity can be corrected by dynamic control of the spatial optical flux profile. Such control is demonstrated through two key innovations: a lamp system in which tungsten-halogen point sources are configured in three concentric rings to provide a circularly symmetric flux profile, and multivariable control whereby each of the three rings is independently and dynamically controlled to provide for control over the spatial flux profile. This approach offers good temperature uniformity over transients, thus improving reliability of individual processes     

An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach     

Mechanical stress as a function of temperature in aluminum films

Mechanical stress in interconnection is a problem of growing importance in VLSI devices. Open circuits due to metal cracking and voiding and short circuits due to hillocks are stress-related phenomena. The origins of this stress are discussed including intrinsic stresses from the synthesis of the films and thermally induced stresses. A measurement technique based on the determination of wafer curvature with a laser scanning device is utilized to directly measure the film stress in situ as a function of temperature during thermal cycling. The changes in stress observed during thermal cycles are interpreted quantitatively and mechanisms that lead to plastic deformation and their relationship to hillocks are discussed. In the stress vs. temperature measurements, several regions have been identified including elastic and plastic behavior both under compression and tension, the yield strength, recrystallization, gain growth, hardening, and solid-state reactions. The effects of deposition conditions on these regions are also examined     

Semi-Empirical Model-Based Multivariable Iterative Learning Control of an RTP System

Comprehensive study on control system design for a rapid thermal processing (RTP) equipment has been conducted with the purpose to obtain maximum temperature uniformity across the wafer surface, while precisely tracking a given reference trajectory. The study covers from model development, identification, optimum multivariable iterative learning control (ILC), to reduced-order controller design. The highlight of the study is the ILC technique on the basis of a semi-empirical dynamic radiation model named as$T^4$-model. It was shown that the$T^4$-model-based ILC technique can remarkably improve the performance of RTP control compared with the ordinary linear model-based ILC. In addition, reduced-order control methods and the associated optimum sensor location have been addressed. The proposed techniques have been evaluated in an RTP equipment fabricating 8-in wafers.     

Model-based emissivity correction in pyrometer temperature controlof rapid thermal processing systems

Single-wavelength pyrometers are most often used to infer wafer temperature in rapid-thermal-processing (RTP) systems. A constant wafer emissivity is assumed with a pyrometer, but a variation in the wafer's surface emissivity can result in an error in the inferred temperature which affects the temperature control of the RTP system. A time-dependent variation is evident in rapid thermal chemical vapor deposition where the emissivity is a function of the film type and thickness. An approach which uses a physically based model of the emissivity variation as part of the feedback control loop is described. The technique employs a first-order model of the emissivity as a function of film thickness from which a projected actual wafer temperature is inferred. The film thickness is approximated using a valid growth-rate expression and temperature as a function of time. These models are then incorporated into the feedback loop of the RTP control system