Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections

An electrical-optical chip input-output (I/O) interconnection technology called sea of polymer pillars (SoPP) is presented. SoPP provides highly process-integrated and mechanically flexible (compliant) electrical-optical die-to-board interconnections that mitigate thermo-mechanical expansion mismatches. The I/O density of SoPP exceeds 10/sup 5//cm/sup 2/. The compliance of the polymer pillars is shown to be 3-5 /spl mu/m/mN. Approximately 50% input optical coupling efficiency into a volume grating coupler through a set of polymer pillars is demonstrated.     

Two-Dimensional Optical Interconnection Based on Two-Layered Optical Printed Circuit Board

The demonstration of an optical platform based on an optical printed circuit board (OPCB) was shown for two-dimensional (2-D) chip-to-chip optical interconnection. The optical platform was designed for 96 Gb/s total throughput which was 2 layers times 4 channels times 4 parallel links times 3 Gb/s/ch and using a passive assembly technology. We fabricated three main components for the 2-D optical interconnection; two-layered six-channel fiber- and connector-embedded OPCB, two-layered six-channel 90deg-bent fiber connectors, and 2-D optical transmitter/receiver (Tx/Rx) modules. The total optical loss from the Tx to the Rx was measured to approximately be -5.3 dB. The optical interconnection using an optical platform was successfully achieved with 3-Gb/s/ch data transmission     

Flexible pillars for displacement compensation in optical chip assembly

In chip-to-chip optical interconnect systems with surface mounted light-sources and detectors, thermal and mechanical effects can cause lateral displacements of the assembled devices. These displacements can result in optical signal losses that can critically deteriorate the bit-error-rate of the digital system. We demonstrate that, for a given loss budget of 1 dB, the use of flexible optical pillars with 150-/spl mu/m height and 50-/spl mu/m diameter can double the lateral displacement tolerance from about 15 to 30 /spl mu/m. The pillars fabricated from Avatrel polymer form an air-free path between the light source and the substrate and cause maximum optical power losses less than 0.2 dB.     

InGaAs光纤探测器封装及耦合效率影响因素研究

设计了InGaAs探测器芯片与多模石英光纤的耦合结构,测试了芯片耦合前后的性能变化,并分析了影响耦合效率的因素。结果表明,石英光纤与InGaAs探测器芯片可以较好地耦合。在0．9-1．7um波段,当采用与芯片尺径相当的100um光纤进行无透镜直接耦合时,耦合效率可达30％以上;当采用芯径为500岫的光纤耦合时,耦合效率可达55％以上。多模石英光纤出射端的光强呈高斯分布。随着光纤端面与芯片表面的间距偏差的增加,高斯分布曲线的半宽值增大,光束逐渐发散。芯片与光纤的对准偏差对耦合效率的影响很大,其中对横向偏移量的依赖性最强。     

Electric-Circuit-Embedded Polymer Optical Bench

In order to overcome the shortcomings of silicon optical bench with surface-patterned electric circuits, an electric-circuit-embedded polymer optical bench was developed. The main design issue was to embed the electric circuit under the optical bench and to let the electric contact pads be opened at the bottom of the alignment pits. To accommodate the surplus conductive adhesive, adhesive-fill space was created at the alignment pits. This architectural invention provides not only more efficient fiber-chip coupling of the planar-lightwave-circuit-type optical waveguide device but also a good electrical contact. An upside-down mounted single-mode waveguide chip showed a coupling loss of about 0.9 dB per coupling face with a single-mode fiber at a wavelength of 1.5 mum     

Rearrangeable Nonblocking 8 × 8 Matrix Optical Switch Based on Silica Waveguide and Extended Banyan Network

Based on the crossbar network and the Banyan network (BN), a new rearrangeable nonblocking structure of extended Banyan network (EBN) was proposed for implementing an 8 times 8 optical matrix switch. The interconnection characteristics of the rearrangeable nonblocking EBN were studied, and the diagram of the logic program for driving the operation of switching units was provided. A silica waveguide 8 times 8 matrix optical switch was designed and fabricated according to the calculated results. The silica waveguide propagation loss of 0.1 dB/cm and waveguide-fiber coupling loss of 0.5 dB/facet were measured. With the fabricated 8 times 8 matrix optical switch, the insertion loss of 4.6 dB, the crosstalk of -38 dB, the polarization-dependent loss of 0.4 dB, the averaged switching power of 1.6 W, and the switching time of 1 ms were achieved. A basic agreement between experimental results and theoretical calculated values was achieved     

Direct Attach of Photonic Components on Substrates With Optical Interconnects

Direct attach of lasers and photodiodes on boards with optical interconnects can facilitate high-density packaging of high-speed optical components. For the technology demonstration, test chips are assembled by means of optical polymer pillars on substrates with embedded arrays of waveguides (WGs) and 45deg mirrors. The light couples vertically though the optical pillars enabling 1.5-dB reduction of the WG-to-chip coupling loss to 0.5dB. The insertion loss of the module tested is less than 2 dB and 10-Gb/s signal transmission through the module is demonstrated with bit-error rate <10^-12. Three-dimensional finite-element analysis provides results on the stress distribution in the displaced pillars of different shapes     

Low-k compatible all-copper flip-chip connections

A novel fabrication technique using electroless copper deposition has been used to produce all-copper, chip-to-substrate connections. This process replaces solder by electrolessly joining copper pillars on the chip and substrate. The electroless copper joints were annealed at 180 °C after plating. A model was developed to explore methods for lowering the stress within the copper pillar, especially at the point where the pillar intersects the chip surface. The acceptable stress level within the copper pillars is a function of the on-chip dielectric material and the on-chip interconnect structures. In order to avoid fracture of the on-chip dielectric, the stress in the copper pillars should be less than the current lead-free solders that the all-copper pillars would be replacing. A polymer collar surrounding the copper pillars was used to support the pillars and improves thermo-mechanical reliability. The improvement in stress-reduction, ultimately leading to higher reliability was studied as a function of elastic modulus of the polymer collar support. It has been shown that the pillar stress generated during temperature cycling can be reduced by increasing the modulus of the pillar support and changing the shape of the copper pillars. Finally, three high-contrast photodefinable collar materials were characterized and tested. Nano-indentation experiments were performed to measure the mechanical properties of each material and shear tests were performed to verify the benefits of the higher elastic modulus collars.     

2$,times,$ 2 InP Optical Switching Matrix Based on Carrier-Induced Effects for 1.55-$mu$m Applications

This letter demonstrates a 2times2 low optical crosstalk and low power consumption switching matrix device based on carrier-induced effects on an InP substrate. The matrix device comprises two digital optical switches (DOSs) with a wide multimode Y-junction associated with a sinusoidal passive integrated optical circuit with an optimized X-crossing. The passive structure was designed using a two-dimensional beam propagation method (BPM) and the entire InP-InGaAsP-InP DOS was designed using a semivectorial three-dimensional BPM. The fabricated 2times2 InP switching matrix heterostructure with lambdag=1.3 mum exhibits optical crosstalk as low as -30.5 dB for drive current of 52 mA at 1.55-mum wavelength. Maximum crosstalk change of 4 dB is measured under optical polarization variation.     

Coupled loops at 20 GHz for stacked planar circuits

Differential planar coupled loops are examined as a method of integrating silicon electronics with passive elements on low-loss microwave laminates. Two test structures are examined which abut planar loops on a CMOS chip to similarly sized loops on a low-loss microwave laminate. The insertion loss of a pair of the 1000times1000 mum loops was measured to be approximately 3 dB at 20 GHz, and the loss between the 700times300 mum loops was measured to be approximately 6 dB at 20 GHz     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

Optical chip-to-chip communication is a promising technology that can mitigate some of the performance short-comings of electrical interconnections, especially bandwidth. Moreover, future high-performance chips are projected to drain hundreds of amperes of supply current. To this end, it is important to develop a high-density and high-performance integrated electrical and optical chip I/O interconnection technology. We describe sea of polymer pillars (or polymer pins), which enables the simultaneous batch fabrication of electrical and optical I/O interconnections at the wafer-level. The electrical and optical I/O interconnections are designed to be laterally compliant to minimize the stresses on the die's low-k dielectric as well as to maintain optical alignment between the coefficient of thermal expansion (CTE)-mismatched board and die during thermal cycling. We demonstrate the fabrication and mechanical performance of various size and aspect ratio electrical and optical polymer pillars. We also describe methods of fabricating polymer pillars with nonflat tip surface area for optical interconnection.     

Fabrication of semiconductor optical switch module using laser welding technique

The 4/spl times/4, 1/spl times/2, and 1/spl times/4 semiconductor optic-switch modules for 1550 nm optical communication systems were fabricated by using the laser welding technique based on the 30-pin butterfly package. For better coupling efficiency between a switch chip and an optical fiber, tapered fibers of 10-15 /spl mu/m lens radius were used to provide the coupling efficiency up to 60%. The lens to lens distance of the assembled tapered fiber array was controlled within /spl plusmn/1.0 /spl mu/m. A laser hammering technique was introduced to adjust the radial shift, which was critical to obtain comparable optical coupling efficiencies from all the channels at the same time. The fabricated optical switch modules showed good thermal stability, with less than 5% degradation after a 200 thermal cycling. The transmission characteristics of the 4/spl times/4 switch module showed good sensitivities, providing error free transmissions below -30 dBm for all the switching paths. The dynamic ranges for the 4/spl times/4 and 1/spl times/2 switch modules were about 8 dB for a 3 dB penalty and about 17 dB for a 2 dB penalty, respectively.     

Bed of Nails—100- $mu$m-Pitch Wafer-Level Interconnections Process

The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-mum pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 mum and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10times10mm²size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40degC to 125degC show promising results.     

Polarization characteristics of index-guided surface-emitting lasers with tilted pillar structure

We report precise control of polarization states for index-guided surface-emitting lasers by tilted-etching of the laser pillar. Circular laser pillars were etched by tilting the substrate toward ~110 or ~11~0 direction with an angle of 15/spl deg/-30/spl deg/ using reactive ion beam etching. For the laser device with a diameter of 7-10 /spl mu/m, we observed selectivity of the polarization state. We found a dominant polarization with an electric field perpendicular to the tilted direction of laser pillar. The maximum orthogonal polarization suppression ratio was about 25 dB. The selectivity of polarization in the tilted laser pillar devices is interpreted to be originated from the difference in optical losses for the two waves polarized to ~110 and ~11~0 directions.     

Integration of 0/1-Level Packaged RF-MEMS Devices on MCM-D at Millimeter-Wave Frequencies

This paper reports on the development and optimization of 0/1-level packaged coplanar waveguide (CPW) lines and radio-frequency microelectromechanical systems (RF-MEMS) switches up to millimeter-wave frequencies. The 0-level package consists of an on-chip cavity obtained by flip-chip mounting a capping chip over the RF-MEMS device using BenzoCyclobutene (BCB) as the bonding and sealing material. The 0-level coplanar RF feedthroughs are implemented using BCB as the dielectric; gold stud-bumps and thermocompression are used for realizing the 1-level package. The 0-level packaged switches have been flip-chip mounted on a multilayer thin-film interconnect substrate using a high-resistivity Si carrier with embedded passives and substrate cavities. The insertion loss of a single 0/1-level transition is below -0.15 dB at 50 GHz. The measured return loss of a 0/1-level packaged 50-Omega CPW line remains better than -19 dB up to 71 GHz and better than -15 dB up to 90 GHz. It is shown that the leak rate of BCB sealed cavities depends on the BCB width, and leak rates as low as 10^-11 mbar.l/s are measured for large BCB widths (> 800 mum), dropping to 10^-8 mbar.l/s for BCB widths of around 100 mum. Depending on the bonding conditions, shear strengths as high as 150 MPa are achieved.     

A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier

This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm². Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P₁ dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P₁ dB is above 10% and the PAE degradation is less than 29%.     

基于端面耦合的InP基激光器/硅光波导混合集成技术研究

针对硅光子集成回路缺少实用化光源的问题,提出了一种1.55μm波段InP基FP激光器芯片、InP基PIN光电探测器芯片与硅光波导芯片集成模块的设计与制备方法。使用CMOS工艺兼容的硅光无源器件制备工艺,设计并制备了倒拉锥型端面耦合器,与锥形透镜光纤耦合效率为36.7%。采用微组装对准技术将激光器芯片与硅波导芯片耦合、UV固化胶固化后耦合效率为35.8%,1 dB耦合对准容差横向为1.2μm,纵向为0.95μm。     

Spot-size converter integrated polarization insensitivesemiconductor optical amplifiers

Spot-size converter integrated polarization-insensitive semiconductor optical amplifier (SSC-SOA) with angled window has been designed and fabricated using both selective area growth and successive lateral tapering. A narrow beam divergence of 80×15°, 0.2-dB amplified-spontaneous-emission ripple, and 1.5-dB polarization sensitivity within the 3-dB optical bandwidth were obtained at 29.7-dB chip gain. The fiber-to-fiber gain of the SOA module was measured to be 22 dB at 200 mA, i.e., the coupling loss was below 4 dB per each facet     

Optical directional coupler using deposited silica waveguides (DS guides)

A new optical directional coupler using embedded single-mode glass waveguides is presented. The glass waveguides, called deposited silica waveguides (DS guides), were fabricated by depositing doped glass on a silica substrate after forming grooves by reactive sputter etching. Waveguide transmission loss was measured to be 1.3 dB/cm, and fiber-to-waveguide coupling loss was 0.1 dB. Using a tunable monochromatic light source, 96 percent power transfer or 14 dB isolation was measured. The DS guide directional coupler is compatible with single-mode fiber and is expected to be a useful component for future wavelength division multiplexing transmission systems.