Low power current-mode voltage controlled oscillator for 2.4 GHz wireless applications

In this paper, a new Complementary Metal Oxide Semiconductor (CMOS) low power Quadrature Voltage Controlled Oscillator (QVCO) based on Chartered 0.18 μm Radio frequency (RF) CMOS technology for 2.4 GHz IEEE 802.11b Wireless Local Area Networks (WLAN) applications is presented. Two explicit quadrature outputs can be realized at high impedance terminals of the QVCO, and it can be cascaded directly to the next stage of a communication system without any matching conditions. The post-layout simulation results show that the oscillation frequency of the QVCO can be tuned from 1.8 GHz to 2.4 GHz by changing the control voltage.     

A New ASIC for Real-Time Linear Color Space Transforms

The design and Very Large Scale of Integration (VLSI) implementation of a new Application Specific Integrated Circuit (ASIC) which converts, in real-time, the Red, Green and Blue (RGB) color coordinates to the XYZ, YIQ and YVU color coordinates, is presented in this paper. Its frequency of operation is 13.3 MHz and the rate of operations of this ASIC is 66.5 MIPS. The high-speed operation is achieved by pipelining the data in a vector fashion. The ASIC is implemented using a Double Layer Metal (DLM), 1.0 μm, N-well, Complementary Metal Oxide Semiconductor (CMOS) process provided by the European Silicon Structures (ES2), and it occupies a silicon area of 6.32 mm × 5.11 mm= 32.29 mm². It is intended to be used in colorimetry instrumentation for color measurement and control, in color machine vision in autonomous applications, where the need for short processing times is crucial and in real-time color image compression applications.     

基于图像处理的手机软板缺陷自动检测方法

针对手机软板缺陷细小难以检测和缺陷不修复的特殊性,研究了一种新型的手机软板缺陷检测方法;系统利用COMS(Complementary Metal 0xide Semiconductor)摄像头获取被测手机软板的图像,通过图像预处理、边缘增强、图像分割得到二值图像;在检测针孔和基板夹杂的缺陷后,去除瑕疵干扰,与标准模板图像进行匹配,得到全局缺陷;再根据设计准则,判断局部缺陷;实验研究表明,这种检测方法检测速度快、精度高,兼顾传统的参考比较法和非参考法的优点,对常见短路、断路、缺口和凸起等缺陷都可以进行精确的检测.     

基于图像视觉伺服的模糊比例积分微分控制系统

针对传统比例积分微分(PID)参数难整定、控制性能不理想等问题,将模糊控制理论与PID控制器相结合,构成模糊PID控制器。采用Eye-to-Hand视觉模型,引入图像视觉伺服机制,通过图像获取误差信号来实现对PID控制器三个参数K_p、T_i和T_d的实时在线自适应调整。最后在以PC机、CompactRIO、NI-9401、互补金属氧化物半导体(CMOS)摄像头、电机驱动器及无刷直流(DC)电机组成的打孔机视觉伺服运动控制系统上完成了实验。结果表明,基于图像的视觉伺服模糊PID控制器相对于传统PID控制器响应速度提高了60%,超调量降低了80%,鲁棒性也更好;不仅能提高孔的定位精度,还能边加工边检测。     

A millimeter‐wave CMOS power amplifier design using high‐Q slow‐wave transmission lines

A three‐stage 60‐GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High‐quality‐factor slow‐wave coplanar waveguides (S‐CPW) were used for input, output and inter‐stage matching networks to improve the performance. Being biased for Class‐A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3‐dB bandwidth of 8.5 GHz. The measured 1‐dB output compression point (OCP_1dB) and the maximum saturated output power P_sat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm² (875 × 600 μm²) including all the pads, whereas the effective area is only 0.24 mm². In addition, the performance improvement of the PA in terms of G, OCP_1dB, P_sat, PAE and the figure of merit using S‐CPW instead of thin film microstrip have been demonstrated. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:99–109, 2016.     

Development of high-accuracy image centroiding algorithm for CMOS-based digital sun sensors

A digital sun sensor calculates the incident sunlight angle using the sunlight image registered on a Complimentary Metal Oxide Semiconductor (CMOS) image sensor. In order to accomplish this, an exact center of the sunlight image has to be determined. Therefore, an accurate estimate of the centroid is the most important factor in digital sun sensor development. The most general method for determining the centroid is the thresholding method, and this method is also the simplest and easy to implement. Another centering algorithm often used is the image filtering method that utilizes image processing. The sun sensor accuracy using these methods, however, is quite susceptible to noise in the detected sunlight intensity. This is especially true in the thresholding method where the accuracy changes according to the threshold level. In this paper, a template method that uses the sunlight image model to determine the centroid of the sunlight image is suggested, and the performance has been compared and analyzed. The template method suggested, unlike the thresholding and image filtering method, has comparatively higher accuracy. In addition, it has the advantage of having consistent level of accuracy regardless of the noise level, which results in a higher reliability.     

电网谐波电压对氧化锌避雷器泄漏电流的影响

采用阻性电流中的基波分量ir和三次分量i3r作为金属氧化锌避雷器(MOA)的监测信号可以及时地发现其老化或劣化现象。但是电网谐波电压将会影响ir、i3r监测的准确性,该文就这种影响进行了详细的仿真研究;并提出了改进的容性电流补偿法,用以求取电网谐波电压情况下的阻性电流。     

Area-Delay-Energy aware SRAM memory cell and M × N parallel read/write memory array design for quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is an emerging nanotechnology, potentially suitable to replace the popular technologies like Complementary Metal Oxide Semiconductor (CMOS) technology. The evolution of QCA has become prominent due to high operating frequency, nanoscale device and zero current low power nanotechnology. However, the Area-Delay-Energy aware QCA logic circuit design remains a prime concern in this post CMOS technology. In this work the primary attention is given to build efficient QCA circuits. The motivation of this work is to propose Efficient VLSI design in terms of Area, Delay, Power and PDP (Power delay product). Different methodologies are reported to design a combinational and sequential circuit in QCA technology. An extensive focus is given in designing of 3 different QCA based Area-Delay-Energy aware SRAM memory cells, parallel read/write M × N SRAM memory array and peripherals like decoder and multiplexer. Since appropriate signal distribution network (SDN) is an essential aspect to deign QCA circuit, it has also been reported a delay aware signal distribution methodology applicable for any type of QCA logic circuit design. The significant results of this research finding are expressed in terms of Area-Delay-Energy dissipation tradeoff. When compared with respective to the state of art, the performance metric of proposed QCA based memory cells are excelled, on an average 40% reduction in area, 33% and 22% drop in delay and energy dissipation respectively are achieved for proposed three different memory cell design.     

应用通道间相关性及增强信息蒸馏的彩色图像去马赛克网络

在商用数码相机中,由于CMOS传感器的限制,在采样得到的图像中的每个像素位置仅有一个色彩通道的信息,因此,需要采用彩色图像去马赛克(CDM)算法来恢复全彩图像.然而,现有的基于卷积神经网络(CNN)的CDM算法不能以较低的计算复杂度和网络参数量取得令人满意的性能.针对这个问题,提出一种应用通道间相关性和增强信息蒸馏(I...     

Novel optimized tree-based stack-type architecture for 2n-bit comparator at nanoscale with energy dissipation analysis

Comparator is an essential building block in many digital circuits such as biometric authentication, data sorting, and exponents comparison in floating-point architectures among others. Quantum-dot Cellular Automata (QCA) is a latest nanotechnology that overcomes the drawbacks of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, novel area optimized 2n-bit comparator architecture is proposed. To achieve the objective, 1-bit stack-type and 4-bit tree-based stack-type (TB-ST) comparators are proposed using QCA. Then, two tree-based architectures of 4-bit comparators are arranged in two layers to optimize the number of quantum cells and area of an 8-bit comparator. Thus, this design can be extended to any 2n-bit comparator. Simulation results of 4-bit and 8-bit comparators using QCADesigner 2.0.3 show that there is a significant improvement in the number of quantum cells and area occupancy. The proposed TB-ST 8-bit comparator uses 2.5 clock cycles and 622 quantum cells with area occupancy of 0.49 µm² which is an improvement by 10.5% and 38%, respectively, compared to existing designs. Scaling it to a 32-bit comparator, the proposed architecture requires only 2675 quantum cells in an area of 2.05 µm² with a delay of 3.5 clock cycles, indicating 9.35% and 28.8% improvements, respectively, demonstrating the merit of the proposed architecture. Besides, energy dissipation analysis of the proposed TB-ST 8-bit comparator is simulated on QCADesigner-E tool, indicating average energy dissipation reduction of 17.3% compared to existing works.

     

Ring Oscillator for 60 Meter Bandwidth

The 60-meter band range is tremendously useful in telecommunication, military and governmental applications. The I. T. U. (International Telecommunication Union) required isolationism to former radio frequency services because the various frequency bands are extremely overloaded. The allocation of new frequency bands are a lengthy procedure as well as time taking. As a result, the researchers use bidirectional, amateur radio frequency communication for 60-meter band, usually the frequency slot of 5250–5450 KHz, although the entire band is not essentially obtainable for all countries. For transmission and reception of these frequencies, a local oscillator is used in the mixer unit to generate the local signal for mixing the input and reference signals. For this function different type of oscillators are used. In this paper, a three-stage ring oscillator is designed with 1 V supply. Ring oscillators (RO) is the base to explore like to identifying, specify with modelling resources in the disparity in behaviour of the circuit in terms of industrialized design and layout parameters. This type of oscillators are free from noise as inductor is not used to the circuit as in LC oscillator, Heartly oscillator, Colpitt and tuned oscillators. The present approach of circuit designing, the scaling of CMOS (Complementary Metal Oxide Semiconductor) transistor will moderate, the procedure variability. In the forthcoming article, a ring oscillator with fixed capacitor (1 pF) and with variable capacitors (1 to 100 pF) is analysed. The frequency analysis with different capacitor is performed. The total delay of 3-stage oscillator is 4.82 ns with 5.2 MHz oscillation frequency. The overall Power dissipation of the circuit is 1.852 μW at 1 V supply. The simulation analysis is performed on 45 nm CMOS technology with both transistor width are 278 and 420 nm.     

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors’ sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.     

Certain investigations in achieving low power dissipation for SRAM cell

The modern semiconductor industry is evolving quite rapidly. Portable and mobile devices are becoming smaller every day and there is also a growing demand for longer battery power. With these demands it is important for researchers to focus on the leakage power in stand-by mode. The SRAM was designed to accurately communicate with CPU, DSP, processor and low-power applications, such as battery-life handheld devices. For some days now, the design engineer focuses mainly on the production of large-capacity memories, high bandwidth and low energy consuming memories. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This Paper Describes the SRAM architecture designed for the reduction of power consumption or power leakages using sleep transistor and MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) techniques. This helps in the reduction of the CMOS transistor leakages. This paper incorporates multiple threshold strategies to give the proposed high speed, increased reliability and low leakage current of the updated 8T SRAM cell in stand-by memory cell mode. Based on the parameters like power dissipation at a different temperature, read voltage, write voltage, read delay, write delay, compared to the previously designed SRAM architecture of 6T, 7T, 8T and 13T we get low power consumption in our designed 8T SRAM architecture. The simulations are conducted with the UMC 55 nm technology Cadence Virtuoso method.     

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.     

New Literature

Semiconductor catalog. A complete listing of Zener diodes, temperature compensated diodes, switching transistors, TransZorb silicon transient voltage suppressors is available from Glenda Kurtz, General Semiconductor Industries, Inc., 2001 West 10th Place, Tempe, AZ 85281; (602) 968-3101.     

A narrative history and description of MOSIS software

This article explores the major software systems used by MOSIS since its inception in 1980, developed by the author. The MOSIS project (Metal Oxide Silicon Implementation System) has served the nation by turning VLSI (microchip) designs, submitted over e-mail, into fully packaged chips, sent back to the user via US mail. Before MOSIS, chip designers were faced with a prohibitive fabrication expense, and the daunting tasks of augmenting their designs with various tedious geometries and coordinating the various vendors ranging from mask making for the fabrication of silicon to packaging. The major innovation has been the “sharing of silicon”. The various “packers” that implement silicon sharing are explored, as well as the other requisite software.     

0.35 μm CMOS–MEMS low-mechanical-noise micro accelerometer

Microsystem Technologies - A CMOS–microelectromechanical systems (MEMS) accelerometer chip produced using Taiwan Semiconductor Manufacturing Company 0.35 μm CMOS technology and...     

Pluronic类化合物水溶液的介观动力学模拟

介观动力学是一种最近发展的动力学密度函数方法,我们将其应用于Ｐｌｕｒｏｎｉｃ类化合物水溶液体系,对该体系中微观相分离动力学过程进行了理论模拟研究。在模拟中,聚合物链（ＰＥＯ）ｘ（ＰＰＯ）ｙ（ＰＥＯ）ｘ被简化为链长相对较短的高斯链,一个单体或几个单体用一个最基本的单元代替,该方法可以直接对聚合物水溶液微观形貌进行三维模拟。和其它平衡理论模拟方法（如蒙特卡罗方法）相比,介观动力学模拟可以给出体系直观的动力学过程,而现在的实验手段尚不能给出体系不稳定过程中的有关信息,所以介观动力学模拟结果将无疑加深我…     

Implementation of cache memory and fir filter using FINFETs at 22 nm technology for SOC designs

The FINFET (Fin field-effect transistors) is projected as a favourable alternative to address challenges faced by continue scaling. Since nanometer procedure schemes are more advanced, the density of chip and frequency of operation have augmented, by making consumption of power in portable devices that are operated by battery could be a significant concern. Though for devices that are non-portable, the consumption of power is significant due to enhanced cooling & packaging costs and possible reliability issues. The metal oxide steady miniaturization semi-conductor field transistor by every novel generation of CMOS (Complementary Metal Oxide Semi-conductor) scheme enhances leakage currents because of minimum channel impacts. The power accounts that are in leakage has been enhancing in a large amount of total consumption of power in deep submicron schemes. Various strategies or schemes are proposes for lessening power leakage. Further, in a system on chip (SOC) designs, caches occupy a significant amount of area in DSP systems, leading to an increase in leakage power. Also, cache memories are used to store filter coefficients. Because of multiple gates, FINFETs structures have better electrostatic control over short channel effects, thus reduces leakage power effectively at the nano regime. In this paper, cache memory and FIR filter are designed by utilizing FINFETs at a 22-nanometer strategy utilizing HSPICE. The experimental outcomes exhibit that structures of FINFET have better leakage control over MOSFET and offers better performance.     

软件定义的无线电提供IoT远程联接

如果不联接,物联网(IoT)和工业物联网(IIoT)就会成为数十亿台设备的集合,其功能和用途有限。互联和联接到云的能力使得这些节点成为我们现在家庭、办公室、工厂和公共场所非常依赖的有用设备。虽然使用有线联接,但在许多情况下,无线技术是首选技术,但各种不同的节点类型和应用意味着没有单一的普遍方案.事实上,方案的数量在增加,包括以标准为导向的技术和在许可和无许可证频谱中运行的协议,以及专有技术。即使如此,情况也在发生变化,因为软件无线电(SDR)提供灵活性,而这种灵活性是纯硬件方案不可能做到的。