Correlation between predicted cause of SRAM failures and in-line defect data

A correlation has been made between the bitmap data from an SRAM and the in-line defect data as measured on a KLA2122 and Tencor7700. The SRAM was a dedicated design for yield enhancement in a 0.35 μm technology. Extra design features were added to encourage the change of having defect on particular places and discourage it on safe designed places. From the failure signature of a memory cell (0 or 1) and its failure extent (single cell, double cell, bitline, wordline (WL), …) one can predict the process-related cause of the failure. A special test program has been written which translates the electrical data from the failing cells into its process defect.The failing bits from the SRAM have been transferred into a KLA results file and added as an extra inspection to the defect database. With a defect source analysis it was possible to find out if the electrical failing bits were seen as a defect in the line and at which steps. With this analysis it is possible to find out if the predicted cause of the process defects from the test program is confirmed by the performed in-line inspections. With an intensive inspection plan about half of the electrical defects were seen in the line. For a large amount of these defects their predicted cause are indeed matching with the inspected layer. Moreover, quite some unknown failures can be explained by the in-line inspections. This correlation work makes it possible to prioritize in tackling the most killing defect sources.     

28 nm低功耗工艺SRAM失效分析

在28 nm低功耗工艺平台开发过程中,对1.26 V测试条件下出现的SRAM双比特失效问题进行了电性能失效模式分析及物性平面和物性断面分析.指出失效比特右侧位线接触孔底部空洞为SRAM制程上的缺陷所导致.并通过元素成分分析确定接触孔底部钨(W)的缺失,接触孔底部外围粘结阻挡层的氮化钛(TiN)填充完整.结合SRAM写操作的原理从电阻分压的机理上解释了较高压下双比特失效,1.05 V常压下单比特不稳定失效,0.84 V低电压下失效比特却通过测试的原因.1.26 V电压下容易发生的双比特失效是一种很特殊的SRAM失效,其分析过程及结论在集成电路制造行业尤其是对先进工艺制程研发过程具有较好的参考价值.     

Localization and physical analysis of a complex SRAM failure in 90nm technology

In this paper the analysis process of a complex SRAM failure in 90nm technology is introduced in detail. Using a correlation method, it could be traced back to a failure with an increased supply current. With the help of MCT emission microscopy and thermal laser stimulation (TLS) the defects were localized at both edges of every failing SRAM block. Further inspection by passive voltage contrast (PVC) and atomic force prober (AFP) current imaging led to a localization down to contact level. In the TEM analysis high angle annular dark field scanning TEM (HAADF STEM) was used to obtain better material contrast. CoSi residues were found at the wall of spacers of the failing FETs. Further surface parallel TEM inspection confirmed the hypothesis of a new type of bridging defect, i.e. CoSi stringers along word lines in SRAM cells, which has not been observed before to our knowledge. The process adjustment in the fab to avoid this failure led to a significant yield improvement. The abstract should be 75-200 words long, summarizing the work and placing it in an appropriate context.     

Temporal and frequency characteristic analysis of margin-related failures caused by an intermittent nano-scale fracture of the solder ball in a BGA package device

This paper analyzes the solder ball fracture that could be a source of intermittent errors. The electrical characteristics of a momentary fracture (open), which may appear at the very beginning of a progressive solder ball failure, are extensively studied. The alternating current (AC)-coupling capacitor is defectively formed because of the fractured solder ball, and it can block low-frequency components of the bit data stream. The distorted signal reduces signal integrity under the fracture and results in increased jitter and reduced eye window. This fracture causes the dropping of the signal voltage level, and this dropping erroneously affects the system when multiple failing conditions are simultaneously satisfied. The major failing condition is the fracture height size, which determines the defective AC-coupling capacitor and changes the channel transmission characteristic. The other major condition is the bit pattern, which includes the frequencies affected by the defective channel. SPICE simulation is conducted to demonstrate the effects of a momentary fracture using the DDR3 memory tester system. In the case of a 10 nm fractured solder ball with a pseudo-random binary sequence (PRBS) pattern, the eye height is reduced from 597 mV to 349 mV, and the jitter is increased from 38 ps to 132 ps. The bits that violate the eye-mask window begin to appear with a heavy bit stream and cause intermittent bit errors.     

Investigation on BIST assisted failure analysis on digital integrated circuits

Built in self tests (BISTs) on integrated circuits are one approach of maintaining fault coverage and device’s testability without increasing the test time. As an additional benefit, for the purpose of failure analysis fault simulation down to node level can be achieved. However, regarding defect localization common FA techniques are still mandatory.In this paper, we present BIST assisted case studies on functional failing integrated circuits. Starting from a fault simulation, defect localization will be done by using conventional failure analysis techniques. After successfully determining the physical defect, we will compare its effect on the affected nodes to the initial fault simulation.     

Investigation on marginal failure characteristics and related defects analysed by soft defect localization

Soft defect localization is a well established failure analysis technique for detecting defects causing integrated circuits to marginal fail. First simulations on Shmoo characteristics using a defect model on simple inverter logic have already been presented. However, the influence of a defect on the Shmoo characteristic for more complex circuit structures is not investigated.This paper discuss a correlation of Shmoo results to both, the defect type and failing circuit structure of a SRAM-cell. Soft defect localization has been applied on two examples showing a bridging defect with a SRAM-cell. In both cases the Shmoo characteristics show a strong voltage dependency. The effect of various bridging defects within a SRAM-cell has been simulated and discussed. With these results the Shmoo characteristic should be considered in the analysis for a defect based on soft defect localization.     

电压衬度像技术在IC失效分析中的应用

电压衬度像(PVC)技术是用于定位集成电路不可见缺陷的一种有效的失效分析方法,结合聚焦离子束(FIB)精准的微切割技术,可将PVC技术应用于长金属互连线的缺陷定位.主要介绍了PVC技术及其原理,概述了如何在SEM和FIB中应用其工作原理有效地定位IC缺陷位置,并就接触孔/通孔缺陷以及规则长金属导线的失效实例展开讨论和分析.     

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm². We designed a 1Mb DRAM with an open bit‐line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when V_cc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.     

Failure analysis of 6T SRAM on low-voltage and high-frequency operation

Careful analysis of SRAM bit failure at high-frequency operation has been described. Using the nanoprober technique, MOS characteristics of failure bit in actual memory cells had been measured directly. It was confirmed that the drain current of a PMOS was about one order in magnitude smaller and the threshold voltage was about 1 V higher than that for normal bits. A newly developed, unique selective etching technique using hydrazine mixture showed these degradations were caused by local gate depletion, and TEM observation showed the PMOS gate poly-Si of the failure bit had a huge grain. Minimizing grain size of the gate poly-Si is found to be quite effective for improving drain current degradation and suppressing this failure mode.     

220kV变电站中刀闸接触缺陷对断路器保护的影响

以一例220kV变电站中出现的刀闸接触缺陷为背景,分析这种缺陷与断路器保护之间存在的关系.文章发现在刀闸接触存在缺陷期间,失灵保护功能与死区保护功能均无法在断路器中得以正常运行,正确动作失真,如无妥善解决,则可能引发事故的进一步扩大.为解决刀闸接触缺陷问题,本文提出具体解决措施,以杜绝此类问题再次出现.     

Investigation of Void Nucleation and Propagation in the Joule Heating Effect During Electromigration in Flip-Chip Solder Joints

This study analyzes the effect of void propagation on the temperature increase of solder joints by using x-ray microscopy, Kelvin probes, and infrared microscopy. It was found that the temperature rise due to void formation was less than 1.3°C when the voids depleted about 75% of the contact opening, even though bump resistance had increased to 10.40 times its initial value. However, the temperature rose abruptly with an increase of up to 8.0°C when the voids depleted 96.2% of the contact opening. A hot spot was observed immediately before the occurrence of open failure in the solder bump. The local increase in temperature was about 30.2°C at the spot. This spot may be the remaining contact area immediately before the occurrence of open failure.     

Layout analysis as supporting tool for failure localization: Basic principles and case studies

To be able to localize a defect on results obtained by failure analysis tools like emission microscopy or OBIRCH analysis it is necessary to understand the effect of a certain defect on an integrated circuit, as only some defects can directly be pinpointed by these analysis methods. In the majority of cases, only second order effects are visible, e.g., a floating gate will cause a transistor to emit light. In that case, the failure site differs from the point of emission.While the physical principles of common defects are well understood one has also to consider the layout of an integrated circuit. By matching the failure analysis results obtained by emission microscopy or OBIRCH analysis to the layout and schematics of a failing device it is possible estimate the root cause of the failure. Thus, the failure site can be narrowed down, to be finally able to proceed with the physical analysis for root cause determination.This paper will give an overview of physical failures that can occur and their effects on emission and OBIRCH analysis. These failure modes will then be correlated to the layout of a device in order to be able to estimate the root cause of a failure based on analysis techniques like emission microscopy and OBIRCH analysis. Finally, we will present case studies of successful failure localization based on layout analysis.     

Exploitation of Laser Voltage techniques for identification and complete characterization of a scan chain transition fail issue using the second harmonic approach

This work presents a Failure Analysis case study related to a scan chain integrity issue. By using Laser Voltage Imaging and Probing (LVx) approaches, we have been able to localize a defect that was inducing a transition failure, detected during scan chain integrity test flow.Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) techniques were applied with the aim of both identifying and characterizing the first failing flip-flop of the chain, in order to understand the failure mechanism.The relatively simple Design For Test (DFT) structure of the device, made of a single scan chain to address a large area of the digital logic, and the nature of the electrical behaviour did not allow the ATPG Scan Chain diagnostic to be accurate, leaving the failure identification task to the FA engineer with the help of classical optical techniques.In this work we specially focused on the application of the two fault isolation techniques, to first, identify the failing flip-flop through dichotomy approach, investigating the macro failure mode through a second harmonic LVI analysis and finally characterizing this failure using LVP.     

Statistical Characterization of Open Failures in the Fine-Pitch COG Interconnection

Chip-on-glass (COG) interconnection using anisotropic conductive film (ACF) is susceptible to open failures. Open failures can be induced by the absence of conductive particles or an insufficient contact. Experimental results as well as statistical approaches were used to understand the conditions for open failures in COG bonding. The binomial distribution was used to predict the probability of the open failure due to the deficiency of conductive particles. The probability of an open failure decreased with increasing bump area and decreasing particle size. The bump height variation was also an important factor that affected the probability of the open failure together with the bump-to-electrode gap and the particle size. The variation in bump height should be minimized to avoid open failures in fine-pitch applications where a smaller particle size is required.     

Open & Short Circuit Reliability of Systems of Identical Items

The paper is about reliability and risk analysis of systems of s-identical, s-independent items in terms of their probabilities of failure in open and short circuit. It is importantly assumed that the system is operational while at least one (or as a special case, more) operational item is connected physically to the input and output of the system either directly or through other good or shorted items and there is no overall system short-circuit. Two or more items so connected, whether in physical series or parallel or any combination have the same effect as a single item, and such redundancy does not alter the item failure probabilities. The probabilities could be those arising from identical, s-independent distributions (iid) over a fixed period with fixed starting conditions or alternatively probabilities of failure upon switching on. The work applies therefore to systems of adjustable or self-adjusting items such as amplifiers, rheostats, or fluid control valves, but not, for example, to systems of fixed resistors if the output values of voltage and current are important. Methods are developed for finding the most reliable physical arrangements of 2, 3, 4, items given the item failure probabilities. These display symmetry arising from the equivalence of the reliability block diagrams for items in physical series failing short and items in physical parallel failing open and vice versa. Three or four items are often sufficient to meet reliability requirements.     

Electromigration in Al/Si contacts—Induced open-circuit failure

Open-circuit failures caused by electromigration in Al/Si contacts are studied. This failure mode is associated with Al depletion or vacancy condensation over the entire position contact area. The contacts exhibiting this failure are those closest to bonding pads. This location preference is attributed to vacancy supplies associated with the large bonding pad. The current acceleration factor for electromigration open failure is found to be 2.5 ± 0.5 and the activation energy is 0.5 ± 0.1 eV. Our empirical data suggests that, for operating temperatures below about 100°C, open-circuit failure will be dominant over junction leakage failure.     

Influence of short circuits on data of contact and via opencircuits determined by a novel weave test structure

Generally test structures containing via strings and contact strings are used to control backend isolation layers' integrity. However, short circuits are the major type of fault resulting from defects during the backend process steps. For this reason, the influence that short circuits have on contact hole open circuits and via hole open circuits in regular string test structures will be investigated here. A novel weave test structure (WTS) is presented to detect open circuits as well as short circuits in adjacent conducting layers of backend process steps. Numerous contact strings or via strings are arranged inside boundary pads like a woven piece of cloth. Thus, short circuits between different strings are also electrically detectable. The separation and localization of defects will be achieved by dividing the chip area into distinguishable subchips inside given standard boundary pads without using any active semiconductor devices. The localization enables a versatile optical defect parameter extraction to precisely determine the reason why and how a defect occurred during the manufacturing process     

基于失效物理的集成电路故障定位方法

超大规模集成电路后道工艺(BEOL)中的失效日益增多,例如多层金属化布线桥连、划伤,栅氧化层的静电放电(ESD)损伤、裂纹等失效模式,由于失效点本身尺寸小加上电路规模大,使得失效分析难度增加。为了能够对故障点进行快速、精确定位,提出了基于失效物理的集成电路故障定位方法。根据CMOS反相器电路的失效模式提出了4种主要故障模型:栅极电平连接至电源(地)、栅极连接的金属化高阻或者开路、氧化层漏电和pn结漏电。结合故障模型产生的光发射显微镜(PEM)和光致电阻变化(OBIRCH)现象的特征形貌和位置特点,进行合理的失效物理假设。结果表明,基于该方法可对通孔缺陷、多层金属化布线损伤以及栅氧化层静电放电损伤失效进行有效的定位,快速缩小失效范围,提高失效分析的成功率。     

90nm技术中接触层Cu扩散缺陷分析与解决方案

在90 nm工艺时代,接触孔工艺问题对于提升90 nm产品的成品率具有重要意义.基于在90 nm工艺中接触孔四周存在的较为严重的Cu扩散问题,通过失效分析,确定引起Cu扩散问题的主要原因是由于光刻胶残留造成的.通过合理的设计,优化了光刻胶清洗流程,最终达到成品率提升的目的.     

Analysis of the p+/p window layer of thin film solar cells by simulation

正The application of a p~+/p configuration in the window layer of hydrogenated amorphous silicon thin film solar cells is simulated and analyzed utilizing an AMPS-ID program.The differences between p~+-p-i-n configuration solar cells and p-i-n configuration solar cells are pointed out.The effects of dopant concentration, thickness of p~+-layer,contact barrier height and defect density on solar cells are analyzed.Our results indicate that solar cells with a p~+-p-i-n configuration have a better performance.The open circuit voltage and short circuit current were improved by increasing the dopant concentration of the p~+ layer and lowering the front contact barrier height.The defect density at the p/i interface which exceeds two orders of magnitude in the intrinsic layer will deteriorate the cell property.