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1.
本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。  相似文献   

2.
Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO2-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.  相似文献   

3.
The effects of electrical stress on hydrogenated n- and p-channel polysilicon thin-film transistors are discussed. The on-state caused the most significant degradation, whereas off-state and accumulation conditions resulted in negligible degradation. The on-state stress degraded the threshold voltage, trap state density, and subthreshold sharpness of both n- and p-channel devices toward perhydrogenated values, and the rates of degradation increased with stressing biases. The field-effect mobility and leakage current, however, were not degraded by stressing. The mechanism of device degradation may be attributed to the metastable creation of midgap states within the polysilicon channel, as opposed to gate dielectric charge trapping or interface state generation  相似文献   

4.
The effect of low-temperature annealing treatment for various durations on the stability of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors was investigated. By this treatment, IGZO TFTs showed enhanced electrical characteristics and better stability under positive gate bias stress with increasing annealing time up to 18,000 s. For all V G stresses at different annealing times, the experimentally measured threshold voltage shift (ΔV th) as a function of stress time was precisely modeled with a stretched-exponential function. ΔV th was generated by carrier trapping, not by defect creation. It was verified that the decrease of interface trap state density (N it) and free carriers resulted in the decrease of ΔV th with increasing annealing time. However, the characteristic trapping time of the carriers increased up to 5.3 × 103 s with increasing annealing time to 7,200 s and then decreased, implying that the interface quality between active layer/insulator was deteriorated with further annealing. In this study, successful fabrication of IGZO TFTs by post treatment with optimized duration is demonstrated for flexible display applications.  相似文献   

5.
Random telegraph signals (RTS) have been investigated in the drain to source voltage of Weff×Leff=1.37×0.17 μm2 medium-doped drain (MDD) n-type MOSFETs. The emission (τe) and capture (τc) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τe and τc including the influence of bulk bias (VSB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO2 interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔVDS/VDS) shows a positive dependence on VSB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.  相似文献   

6.
The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between VGS=0 V and VGS=VDS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (IGmax). In the case of VGS corresponding to IGmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from VGS=VGS@IGmax to VGS=VDS.  相似文献   

7.
Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (VGS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all VGS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (ΔVth) as a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the ΔVth is generated by carrier trapping but not defect creation. It is also observed that the ΔVth shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (NT) and free carriers resulted in the increase of ΔVth as the channel layer thickness increases.  相似文献   

8.
9.
In some automotive applications, high negative bias is used to faster switch off n-type devices. This exceptional operative gate voltage at relative high temperature can induce instability of device parameters (e.g. threshold voltage, transconductance, saturation current, etc.In this work we will show that positive charge trapping generated under exceptional negative bias can induce large threshold voltage shift. Even if the effect can partially recover during the standard operative condition, nevertheless large Vth, shift are still present and can affect the correct functionality of the device.  相似文献   

10.
Electrical measurements of voltage stressed Al2O3/GaAs MOSFET   总被引:1,自引:0,他引:1  
Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al2O3 gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current (Ig) on the gate voltage (Vg) was found to fit the CVS data of the low positive Vg range. The percolation model well explains the degradation of Ig after a high positive Vg stress. A positive threshold voltage (Vth) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al2O3 layer during the initial CVS, while the trapping of electrons by existing traps in the Al2O3 layer is responsible for the Vth shift during the subsequent CVS.  相似文献   

11.
We investigated the effect of photon irradiation with various energies on the gate bias instability of indium-gallium-zinc oxide transistors. The illumination of red and green light on the transistor caused positive threshold voltage (Vth) shifts of 0.23 V and 0.18 V, respectively, while it did not affect the Vth value in blue light after a positive bias stress. However, the stability of transistors was deteriorated with increasing photon energy after a negative bias stress: negative Vth shifts for red (−0.23 V) and blue light (−3.7 V). This difference can be explained by the compensation effect of the electron carrier trapping and the creation of meta-stable donors via photon excitation.  相似文献   

12.
Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for VFB < VG < 0 V and the second for VG < VFB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.  相似文献   

13.
Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiNx as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress (VG = 25 V, VD = 0), (ii) on-state bias stress (VG = 25 V, VD = 20 V) and (iii) off-state bias stress (VG = −25 V, VD = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.  相似文献   

14.
In this work we point out the importance of the device parameter Vg,max-Vth (the difference between the gate voltage at maximum transconductance and the threshold voltage obtained from linear extrapolation method) for LTPS TFTs under dc stress. The evolution of this parameter with stress time is monitored for the first time, along with the other typical device parameters (VthGm,maxS) in order to further clarify the nature of the traps generated. In the first dc stress case considered, we observed very different S degradation of the two samples, but very similar Gm,max degradation, as well as similar Vg,max-Vth evolution. Therefore, Gm,max evolution with stress time was found to be related more strongly to tail state generation, probed through Vg,max-Vth, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail state generation. Hence, the nature of the created defects and the reason for the significant Gm,max reduction could only be probed through the observation of Vg,max-Vth, a parameter not utilized until now. Finally, stressing both n- and p-channel devices, we are able to explain the much more intense Gm,max degradation observed for n-channel devices, associating it to the larger tail state generation in n-channel TFTs, also pointed by Vg,max-Vth evolution with stress.  相似文献   

15.
Effects of electrical stressing in power VDMOSFETs   总被引:2,自引:2,他引:0  
The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Sis–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Sis–H with the charged oxide traps and H+ ions are proposed to be responsible for interface trap buildup.  相似文献   

16.
The decrease of the threshold voltage Vth of p-channel metal-oxide semiconductor field effect transistors (p-MOSFET) with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed, that accounts for the generation of Si3Si (Pb0) centers and bulk oxide defects, induced by the tunnelling of electrons or holes through the gate dielectric layer during the electrical stress. The model predicts that Vth shifts are mainly due to the tunnelling of holes at low gate bias |VG|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |VG|. Consequently, device lifetime at operating voltage, based on Vth shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on Vth shifts is next investigated. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si---N---Si strained bonds, that act as trapping centers of hydrogen species released during the electrical stress. Finally, Vth shifts in p-MOSFET with HfySiOx gate layers and SiO2/HfySiOx gate stacks are simulated, taking into account the generation of Pb0 centers induced by the injection of electrons through the structure. It is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO2/HfySiOx gate stacks as compared to single HfySiOx layers. This finding is attributed to the beneficial presence of the SiO2 interfacial layer, which allows the relaxation of strain at the Si/dielectric interface.  相似文献   

17.
We investigated the air stabilities of threshold voltages (Vth) on gate bias stress in pentacene thin-film transistors (TFTs) with a hydroxyl-free and amorphous fluoropolymer as gate insulators. The 40-nm-thick thin films of spin-coated fluoropolymer had excellent electrical insulating properties, and the pentacene TFTs exhibited negligible current hysteresis, low leakage current, a field-effect mobility of 0.45 cm2/Vs and an on/off current ratio of 3 × 107 when it was operated at −20 V in ambient air. After a gate bias stress of 10s, a small Vth shift below 1.1 V was obtained despite non-passivation of the pentacene layer. We have discussed that the excellent air stability of Vth was attributed to the insulator surface without hydroxyl groups.  相似文献   

18.
In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μFE> 1 cm2V−1s−1) and excellent stability under gate bias stress (bias stress Vds = 0V). However, after prolonged bias stress performed at high drain voltage, Vds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high Vds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.  相似文献   

19.
The hysteresis effect between forward and reverse drain-source voltage (VDS) sweeps in the transient output characteristics is studied in ultra-thin gate oxide floating-body partially depleted (PD) silicon-on-insulator (SOI) n-MOSFETs. In this study, two mechanisms including direct-tunneling and impact ionization are taken into account. The transient variation of the floating body potential during sweeps leads to the threshold voltage (VTH) unstable, hence the hysteresis delay occurs. It is proposed that hole tunneling from valence band (HVB) causes positive hysteresis at lower drain-source voltage (VDS) region, while impact ionization (II) induced floating body charging leads to opposite phenomenon at high VDS, thus causing threshold voltage unstable in drain bias switching. And our findings reveal that hysteresis effect can be a serious reliability issue in SOI devices with floating body configuration.  相似文献   

20.
《Microelectronics Journal》2007,38(6-7):727-734
This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO2 barrier.  相似文献   

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