Hot-carrier reliability of submicron NMOSFETs and integrated NMOS low noise amplifiers

The effects of hot-carrier stress (HCS) on the performance of NMOSFETs and a fully integrated low noise amplifier (LNA) made of NMOSFETs in a 0.18 μm CMOS technology are studied. The main effects of HCS on single NMOSFETs are an increase in threshold voltage and a decrease in channel carrier mobility, which lead to a drop in the biasing current of the transistors. In the small-signal model of the transistor, hot-carrier effects appear as a decrease in the transconductance and an increase of the output conductance. No clear change was observed in the parasitic gate–source and gate–drain capacitances in the devices under test due to hot carriers. The main effects of hot carriers in the LNA were a drop of the power gain and an increase of its noise figure. The input and output matching, S₁₁ and S₂₂, slightly increased after hot-carrier stress. The third- order input-referred intercept point (IIP3) of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the current–voltage (I–V) characteristics of the transistors in the LNA at the particular operating point where they were biased.     

Comparative analysis of RF LDMOS capacitance reliability under accelerated ageing tests

This paper presents the results of comparative reliability study of C–V characteristics through three accelerated ageing tests for stress applied to an RF LDMOS: Thermal shock tests (TST, air–air test), thermal cycling tests (TCT, air–air test) and high temperature storage life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The investigation findings of electrical parameter degradations after various ageing tests are discussed. Feedback capacitance (Crs) is reduced by 16% and gate–drain capacitance (Cgd) by 42%. This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. A physical simulation software has been used to confirm qualitatively degradation phenomena.     

Hot-carrier induced series resistance enhancement model (HISREM) of nMOSFET's for circuit simulations and reliability projections

This paper proposes a physically realizable reliability model of nMOSFET's that is applicable for reliability projections in IC design. We have devised a hot-carrier induced series (drain) resistance enhancement model (HISREM) which is based on the increase of the interface trapped charge (ΔNit) near the drain region and is physically realizable in circuit simulations of the hot-carrier induced degradation under operating conditions. The proposed HISREM requires only one parameter (ΔNit) for reliability projections in IC design without extraction of a set of stressed parameter files. The proposed HISREM s shows a good agreement between the simulation results from SPICE and experiment data of the hot-carrier induced degradation of device characteristics. The HISREM has been demonstrated by employing a NMOS inverter and a conventional CMOS operational amplifier. The HISREM is shown to be much simpler and more efficient for reliability projections in both digital and analog IC design rather than the commercial reliability simulator with parameter degradation models which require extraction of a set of stressed parameter files (i.e., Vto, γ, μ_o, θ, V_max, ).     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

The effects of buffer thickness on GaAs MESFET characteristics: channel–substrate current, drain breakdown, and reliability

The effects of thickness in metal–semiconductor field effect transistor (MESFET) GaAs buffer on the device electrical performance and reliability have been investigated. Devices studied are 0.8-μm-gate GaAs MESFETs at different buffer thickness of 0.5 and 0.3 μm from similar MBE-grown processes. Three-terminal off-state breakdown measurements indicate that a substantial enhancement in the observed breakdown current for thinner-buffer MESFETs is attributed to the drain–source leakage or breakdown through the channel–substrate interface while the device is at pinch-off. DC and RF biased stress lifetests up to 323 °C channel temperature have been performed to accelerate the degradation mechanisms. It is found that the device degradation rate has little dependence on buffer thickness when stressed at a reversed gate–drain voltage below 70% of its breakdown threshold. The differences grow rapidly when biased close to the breakdown field because of the development of channel–substrate current in thinner buffer materials.     

Lifetime reliability of thin-film SOI nMOSFET's

The dc device lifetime reliability of thin-film SOI MOSFET's is investigated over a wide range of drain stress from just below the SOI breakdown voltage up to typical accelerated stress voltages. Unique hot-carrier degradation behaviors were observed for different ranges of applied drain stress. The degradation behavior and mechanism are found to dynamically change from one type observed under low drain stress (realistic operation range) to a different type observed under high drain stress (strong breakdown operation). This causes the SOI MOSFET to exhibit a two slope lifetime versus reciprocal drain voltage behavior which could have strong implications on the hot-carrier stressing methodology and reliability study of these devices     

Design considerations for CMOS digital circuits with improvedhot-carrier reliability

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (τ) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability     

Hot-carrier reliability in deep-submicrometer LATID NMOSFETs

The hot-carrier degradation of large angle tilt implanted drain (LATID) NMOSFETs of a 0.35 μm CMOS technology is analysed and compared to the degradation behaviour of standard LDD devices. LATID NMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity. By means of I–V characterisation and charge pumping measurements, the different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I–V susceptibility to a given amount of generated damage.     

Hot-carrier effects in scaled MOS devices

A universal guideline and state-of-the-art hot-carrier effects in scaled MOSFETs are reviewed and discussed from the viewpoints of 1) DC and AC hot-carrier effects, 2) hot-carrier detrapping phenomena, 3) mechanical stress effects on hot-carrier phenomena, and 4) hot-carrier resistant device structures.In the deep-submicron region, the hot-carrier applicable voltage is less than 3 V, so AC hot-carrier effects from the dynamic operation of actual circuits should be taken into account. Despite much experimentation and analysis, there is still no universally accepted theory that explain the AC degradation mechanism. This is because the noise caused by the wiring inductance in ULSI circuits and in measurement systems screens the intrinsic AC hot-carrier effects.Here, AC hot-carrier degradation enhanced by gate pulse-induced-noise is analyzed experimentally and theoretically. After eliminating the noise problem, it is found that AC hot-carrier degradation in LDD (Lightly doped drain) and GOLD (gate-drain overlapped device) structures can be estimated based on DC degradation in terms of the effective stress time which takes the duty ratio into account. In addition, it is found that the noise is negligible when the wiring inductance is smaller that 80 nH (250 mω), which is important for future circuit design.Furthermore, hot-carrier detrapping effects, especially in p-channel MOS devices, and hot-carrier phenomena under mechanical stress are investigated experimentally to better understand the underlying hot-carrier physics. Finally, future hot-carrier resistant device structures are discussed.     

Analysis of high temperature effects on performances and hot-carrier degradation in DC/AC stressed 0.35 μm n-MOSFETs

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25–125 °C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. Different degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what effectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 °C using inverter and pass transistor operations in a 0.35 μm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation.     

Suppression of hot-carrier effects in submicrometer CMOS technology

Approaches used to suppress the hot-carrier effects in submicrometer CMOS technology based on the drain engineering of the device structure and process-induced deice degradation are discussed. Different types of lightly doped drain (LDD) structures are studied. Several process-related device aging issues are discussed. Twin-Tub V CMOS technology is used as an example of how to manage the hot-carrier issues with respect to the process integration aspects     

Continuous analytic I–V model for GS DG MOSFETs including hot-carrier degradation effects

We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET device. Our analysis is carried out by using an accurate continuous current-voltage (I-V) model, derived based on both Poisson's and continuity equations without the need of charge-sheet approximation. The developed model offers the possibility to describe the entire range of different regions (subthreshold, linear and saturation) through a unique continuous expression. Therefore, the proposed approach can bring considerable enhancement at the level of multi-gate compact modeling including hot-carrier degradation effects.     

A new approach for characterizing structure-dependent hot-carriereffects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N_it ) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N_it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N_it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices     

Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (T_ox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with T_ox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.     

Effects of source/drain implants on short-channel MOSFET I-V andC-V characteristics

The effects of source/drain implants on n-channel MOSFET I-V and C-V characteristics are measured and compared for the lightly doped drain (LDD) and the large-angle-tilt implanted drain (LATID) devices. We show that despite substantial improvement in hot-carrier reliability for LATID devices, the LATID design might have a limited range of application for short-channel MOSFETs. This is because as a result of enhanced V_TH roll-off and increased overlap capacitance for the LATID devices compared to LDD devices, the device/circuit performance degrades. The degradation of performance becomes more pronounced as device length is reduced. These results are confirmed by both experimental data and 2-dimensional numerical simulations     

An As-P(n+-n-)double diffused drain MOSFET for VLSI's

An As-P(n⁺-n^-) double diffused drain is characterized as one of the most feasible device structures for VLSI's from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10^-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.     

A comparison of hot-carrier degradation in tungsten polycide gateand poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n⁺ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi_x p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C_gd^s measurement shows increased susceptibility to electron trapping in the WSi_x device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on ΔV_t=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 μm, the reduced hot-carrier lifetime of WSi_x p-MOSFETs suggests that WF₆-based silicidation may not be appropriate for deep submicrometer CMOS devices     

On the InGaP/InxGa1−xAs pseudomorphic high electron-mobility transistors for high-temperature operations

The high-temperature characteristics of a novel InGaP/In_xGa_1−xAs pseudomorphic transistor with an inverted delta-doped channel are reported. Due to the presented wide-gap InGaP Schottky layer and the V-shaped In_xGa_1−xAs channel structure, the degradation of device performance with increasing the temperature is not so significant. Experimentally, for a 1×100 μm² device, the gate–drain voltages at a gate leakage current of 260 μA/mm and the maximum transconductances g_m,max are 30 (22.2) V and 201 (169) mS/mm at the temperature of 300 (450) K, respectively. Meanwhile, broad and flat drain current operation regimes for g_m, f_T and f_max are obtained.     

Experimental evidence for nonlucky electron model effect in 0.15-/spl mu/m NMOSFETs

It is shown that in 0.15-/spl mu/m NMOSFETs the device lifetime under channel hot-carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-/spl mu/m NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to increased interface state generation by the movement of the maximum impact ionization site from the lightly doped drain (LDD) diffusion region to the boundary of the bulk and LDD region beneath the gate oxide. This paper provides experimental evidence for the non-LEM effect by comparing the degradation characteristics and the maximum impact ionization sites as a function of gate oxide thickness and gate length.