优化时延与拥挤度的增量式布局算法

提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10%.     

微电子学、集成电路

TN4 2004050515优化时延与拥挤度的增t式布局算法/李卓远,吴为民,洪先龙(清华大学)”半导体学报一2 004,25(2)一158一164提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10%图3表3参15(木)的散射参数解析表达式,给出了…     

基于整数规划的优化拥挤度的增量式布局算法

提出了一种降低走线拥挤的标准单元增量式布局算法C-ECOP.首先通过一种新型的布线模型来估计芯片上的走线情况,然后构造一个整数线性规划问题来解决可能出现的相邻拥挤区域冲突问题.实验结果表明该算法能够有效地降低走线拥挤,保证初始布局的质量,并且具有很高的效率.     

基于整数规划的优化拥挤度的增量式布局算法

提出了一种降低走线拥挤的标准单元增量式布局算法C- ECOP.首先通过一种新型的布线模型来估计芯片上的走线情况,然后构造一个整数线性规划问题来解决可能出现的相邻拥挤区域冲突问题.实验结果表明该算法能够有效地降低走线拥挤,保证初始布局的质量,并且具有很高的效率     

正态分布评价方式的布局拥挤度优化方法

在传统布局算法中,一般优化目标只考虑线长和时序两个因素.而实际情况下,布局拥挤度在很大程度上会影响布线效率,从而影响最终设计质量.为了更好地模拟实际设计的应用情况,基于模拟退火布局算法,提出了一种基于正态分布拥挤度的评估模型.该模型通过将拥挤度用数学模型建模的方式形成代价函数,并将该代价函数的形式拟合到原有的评价函数中...     

一种新的标准单元增量式布局算法

提出了一种新的增量式布局方法W-ECOP来满足快速调整布局方案的要求.与以前的以单元为中心的算法不同,算法基于单元行划分来进行单元的插入和位置调整,在此过程中使对原布局方案的影响最小,并且尽可能优化线长.一组从美国工业界的测试例子表明,该算法运行速度快,调整后的布局效果好.     

一种新的标准单元增量式布局算法

提出了一种新的增量式布局方法W-ECOP来满足快速调整布局方案的要求.与以前的以单元为中心的算法不同,算法基于单元行划分来进行单元的插入和位置调整,在此过程中使对原布局方案的影响最小,并且尽可能优化线长.一组从美国工业界的测试例子表明,该算法运行速度快,调整后的布局效果好.     

一种新的基于查找表的时钟性能驱动的增量式布局算法

提出了一种新的时钟性能驱动的增量式布局算法,它针对目前工业界较为流行的标准单元布局,应用查找表模型来计算延迟.由于在布局阶段较早地考虑到时钟信息,可以通过调整单元位置,更有利于后续的有用偏差时钟布线和偏差优化问题.来自于工业界的测试用例结果表明,该算法可以有效地改善合理偏差范围的分布,而对电路的其它性能影响很小.     

一种新的基于查找表的时钟性能驱动的增量式布局算法

提出了一种新的时钟性能驱动的增量式布局算法,它针对目前工业界较为流行的标准单元布局,应用查找表模型来计算延迟.由于在布局阶段较早地考虑到时钟信息,可以通过调整单元位置,更有利于后续的有用偏差时钟布线和偏差优化问题.来自于工业界的测试用例结果表明,该算法可以有效地改善合理偏差范围的分布,而对电路的其它性能影响很小.     

标准单元模式下的一种时钟驱动增量式布局算法

增量式布局是适应高性能布局设计要求而出现的一种新型布局方法。本文针对时钟设计中的有用偏差时钟布线问题，提出了一种标准单元模式下时钟性能驱动的增量式布局算法CEP。该算法通过局部调整单元位置，重新获得合理的布局，从而降低触发器单元对时钟信号同步性的要求。通过对实际电路的测试，表明CEP算法可以在不破坏原有布局性能参数的前提下，有效地改善触发器单元之间的合理偏差范围，有利于后续的时钟布线。     

一种新的基于单元扩大的拥挤度驱动的布局算法

描述了一种新的基于单元扩大的拥挤度驱动的布局算法 .这个方法用概率估计模型和星型模型来评价线网的走线 .使用全局优化和划分交替的算法来进行总体布局 .提出了单元的虚拟面积的概念 ,单元的虚拟面积不仅体现了单元的面积 ,而且指出了对布线资源的需求 .单元的虚拟面积可以由单元的扩大策略来得到 .把单元的虚拟面积用到划分过程中 ,从而减小拥挤度 .并且使用了单元移动的策略来进一步减小走线的拥挤 .用来自美国公司的一些例子测试了这个算法 ,结果显示布局的结果在可布性方面有了很大的提高     

Wire congestion estimation in a bounded-bend model

Interconnect congestion estimation plays an important role in the physical design of integrated circuits. Fast congestion analysis prior to global routing enhances the placement quality and improves the routability for the subsequent routing phases. This article presents a novel congestion estimation method for a wire layout with bounded detours and bends. Experimental results on benchmarks demonstrate the efficiency and accuracy of our approach.     

A fast congestion estimator for routing with bounded detours

Congestion estimation is an important issue for design automation of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach that allows wires to have bounded-length detours to bypass congestions. The method is more realistic and precise than the previous work. The experimental results demonstrate the effectiveness of the method on routing benchmarks.     

一种新的基于单元扩大的拥挤度驱动的布局算法

描述了一种新的基于单元扩大的拥挤度驱动的布局算法．这个方法用概率估计模型和星型模型来评价线网的走线．使用全局优化和划分交替的算法来进行总体布局．提出了单元的虚拟面积的概念,单元的虚拟面积不仅体现了单元的面积,而且指出了对布线资源的需求．单元的虚拟面积可以由单元的扩大策略来得到．把单元的虚拟面积用到划分过程中,从而减小拥挤度．并且使用了单元移动的策略来进一步减小走线的拥挤．用来自美国公司的一些例子测试了这个算法,结果显示布局的结果在可布性方面有了很大的提高．     

一个同时考虑时延约束和拥挤度优化的总体布线新方法

文章介绍了一个可以同时考虑时延约束和拥塞度优化的VLSI总体布线新方法。文章引入软边和滑动斯坦那点的概念，使布线的拓扑结构具有灵活性，使得总体布线在满足时延约束的情况下，可以有效缩减线网的拥塞度。     

Evaluation,prediction and reduction of routing congestion

Routing congestion is a critical issue in deep submicron design technology and it becomes one of the most challenging problems in today's design flow. In this paper, various congestion-related metrics were defined and evaluated during placement stage of physical design flow. Our experiments show that the overflow metric results are more accurate than others. In addition, the bend distributions after detailed routing for IBM-PLACE benchmarks were extracted and used to guide a pure probabilistic method. Furthermore, router's behavior for congestion minimization was modeled and used to propose a true congestion prediction algorithm. Experimental results show that the proposed algorithm estimates the congestion more accurately than a commonly used method by about 21% on average. Additionally, a new congestion reduction algorithm is presented based on contour plotting. Our experiments show that our algorithm reduces the peak congestion by about 25% on average. In addition, comparing our results with a recent approach shows that our technique reduces congestion more by about 10% on average. In order to evaluate the results of white space allocations on the quality of our reduction technique, several other experiments were attempted. Various amounts of white space were added to several IBM-PLACE benchmarks and the contour plotting-based reduction technique was used to reduce the peak and average congestion. The experiments show that our technique works better on the benchmarks with more white space as it has more capability to distribute routing congestion evenly.     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

An algorithm is presented for obtaining placements of cell-based very large scale integrated circuits, subject to timing constraints based on table-lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well-known quadratic placement with bottom-up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.