A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

A novel CMOS operational transconductance amplifier based on a mobility compensation technique

This brief describes a new linear operational transconductance amplifier (OTA) and its application to a ninth-order Bessel filter. To improve the linearity of the OTA, we employ a mobility compensation circuit which combines the transistors operating in the triode and the subthreshold regions. The proposed technique enhances the linearity of the transconductance without loss of the input swing range. The proposed OTA shows /spl plusmn/0.5% Gm variation and the total harmonic distortion of less than - 60-dB over the input range of /spl plusmn/0.8-V. The ninth-order Bessel filter employing the proposed OTA has been implemented in a 0.35-/spl mu/m n-well CMOS process under 3.3-V supply voltage. It shows the cutoff frequency of 8 MHz and the power consumption of 65 mW.     

A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communication

The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well as a fast-settling folded-cascode amplifier. These techniques are applied to an experimental fifth-order elliptic SC filter fabricated in a 2-/spl mu/m CMOS technology. The experimental results show that a 3.6-MHz cutoff frequency is attained. All the capacitors are scaled down in order to reduce the setting time of the amplifiers. The active area of the filter is 0.9 mm/SUP 2/. The F/SUB sampling//F/SUB cutoff/ is only 5. The circuit operates from /spl plusmn/5 V and typically dissipates 80 mW when sampled at 18 MHz.     

Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz

An enhanced configuration for a linearized MOS operational transconductance amplifier (OTA) is proposed. The proposed fully differential OTA circuit is based on resistive source degeneration and an improved adaptive biasing technique. It is robust to process variation, which has not been fully shown in previously reported linearization techniques. Detailed harmonic distortion analysis demonstrating the robustness of the proposed OTA is introduced. The transconductance gain is tunable from 160 to 340 /spl mu/S with a third-order intermodulation (IM3) below -70 dB at 26 MHz. As an application, a 26-MHz second-order low-pass filter fabricated in TSMC 0.35-/spl mu/m CMOS technology with a power supply of 3.3 V is presented. The measured IM3 with an input voltage of 1.4 Vpp is below - 65 dB for the entire filter pass-band, and the input referred noise density is 156nV//spl radic/Hz. The cutoff frequency of the filter is tunable in the range of 13-26 MHz. Theoretical and experimental results are in good agreement.     

A micropower fourth-order elliptical switched-capacitor low-pass filter

A micropower fourth-order elliptical switched-capacitor (SC) low-pass filter for biomedical applications has been designed and measured. The charge transfer error of an SC integrator using a transconductance amplifier is discussed. Also first-order noise and PSRR calculations are performed and compared with the results of simulations and measurements. The measurements show that by careful optimization of the gain bandwidth, slew rate, and gain of the amplifiers, high-performance low-power SC filters can be constructed. The cutoff frequency of the filter is 5 kHz, the ripple in the passband is 0.27 dB, and stopband rejection is 49 dB. The power consumption of the filter is 190 /spl mu/W with /spl plusmn/2.5-V power supplies. The dynamic range of the filter is 75 dB, and the total harmonic distortion over the whole passband range is below 0.25% for a 2-V/SUB pp/ input signal. The PSRR of the filter is above 40 dB at frequencies below 3 kHz.     

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

The design of a 2.4-GHz fully integrated /spl Sigma//spl Delta/ fractional-N frequency synthesizer in a 0.35-/spl mu/m CMOS process is presented. The design focuses on the prescaler and the loop filter, which are often the speed and the integration bottlenecks of the phase-locked loop (PLL), respectively. A 1.5-V 3-mW inherently glitch-free phase-switching prescaler is proposed. It is based on eight lower frequency 45/spl deg/-spaced phases and a reversed phase-switching sequence. The large integrating capacitor in the loop filter was integrated on chip via a simple capacitance multiplier that saves silicon area, consumes only 0.2 mW, and introduces negligible noise. The synthesizer has a 9.4% frequency tuning range from 2.23 to 2.45 GHz. It dissipates 16 mW and takes an active area of 0.35 mm/sup 2/ excluding the 0.5-mm/sup 2/ digital /spl Sigma//spl Delta/ modulator.     

Differential current-mode tunable wave active filters based on single-ended wave port terminators

A method for the design of differential current-mode wave active filters, which is based on the use of single-ended wave port terminators, is presented in this paper. The resulting filters are modular and very simple to design while their cutoff frequency is controlled by a dc current, giving them the ability of frequency tuning. As an example a wide-band bandpass filter is realized by cascading a low-pass and a highpass filter. The overall filter has been integrated using a standard 0.35-/spl mu/m CMOS technology.     

Current-mode integrator for voltage-controllable low frequency continuous-time filters

A novel differential current-mode integrator (CMI) for voltage-controllable low frequency continuous-time filters is presented. An example fifth-order lowpass filter using the proposed CMI and on-chip capacitors was implemented in an AMI 1.2 /spl mu/m CMOS process, and it achieved -3 dB cutoff frequencies ranging from 160 Hz to 5.6 kHz, by changing a single control voltage.     

A G/sub m/-C low-pass filter for zero-IF mobile applications with a very wide tuning range

A third-order G/sub m/-C Butterworth low-pass filter implementing G/sub m/-tuning and G/sub m/-switching to maximize the tuning range is described. This filter is intended to be used as a channel-selection/anti-aliasing filter in the analog baseband part of a zero-IF radio receiver architecture for multimode mobile communications. Its G/sub m/-switching feature allows extending the tuning range and adapting the power consumption. The filter's cutoff frequency ranges from 50 kHz to 2.2 MHz. An Input IP3 of up to +18 dBV/sub p/ is achieved, for a total worst-case power consumption of 7.3 mW for both I and Q paths, and an effective area of less than 0.5 mm/sup 2/ in a 0.25-/spl mu/m SiGe BiCMOS process. A new figure of merit is introduced for comparison of published low-pass tunable filters including noise, linearity, and tuning range.     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

Current-mode differential wave active filters

A technique for obtaining differential active filters suitable for integrated circuit implementation is presented. These filters, based on current-mode differential-wave active blocks, can operate at high frequencies. The cutoff frequency can by tuned by the bias current. The proposed filter topologies are modular and very flexible for both the electronic and the physical design. Simulation results of a third-order elliptic filter, designed in a 0.35-/spl mu/m CMOS technology, are presented.     

Miniature and tunable filters using MEMS capacitors

Microelectromechanical system (MEMS) bridge capacitors have been used to design miniature and tunable bandpass filters at 18-22 GHz. Using coplanar waveguide transmission lines on a quartz substrate (/spl epsiv//sub r/ = 3.8, tan/spl delta/ = 0.0002), a miniature three-pole filter was developed with 8.6% bandwidth based on high-Q MEMS bridge capacitors. The miniature filter is approximately 3.5 times smaller than the standard filter with a midband insertion loss of 2.9 dB at 21.1 GHz. The MEMS bridges in this design can also be used as varactors to tune the passband. Such a tunable filter was made on a glass substrate (/spl epsiv//sub r/ = 4.6, tan/spl delta/ = 0.006). Over a tuning range of 14% from 18.6 to 21.4 GHz, the miniature tunable filter has a fractional bandwidth of 7.5 /spl plusmn/ 0.2% and a midband insertion loss of 3.85-4.15 dB. The IIP/sub 3/ of the miniature-tunable filter is measured at 32 dBm for the difference frequency of 50 kHz. The IIP/sub 3/ increases to >50 dBm for difference frequencies greater than 150 kHz. Simple mechanical simulation with a maximum dc and ac (ramp) tuning voltages of 50 V indicates that the filter can tune at a conservative rate of 150-300 MHz//spl mu/s.     

Switched-current circuits in digital CMOS technology with low charge-injection errors

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.     

A 2-V/sub pp/ 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning

A CMOS 80-200-MHz fourth-order continuous-time 0.05/spl deg/ equiripple linear phase filter with an automatic frequency tuning system is presented. An operational transconductance amplifier based on transistors operating in triode region is used and a circuit that combines common-mode feedback, common-mode feedforward, and adaptive bias is introduced. The chip was fabricated in a 0.35-/spl mu/m process; filter experimental results have shown a total harmonic distortion less than -44 dB for a 2-V/sub pp/ differential input with a single 2.3-V power supply. The group delay ripple is less than 4% for frequencies up to 1.5 f/sub c/. The frequency tuning error is below 5%.     

A 48-16-MHz CMOS SC decimation filter

This paper presents a CMOS switched-capacitor decimation filter for prefiltering operations in video communications systems, reducing the complexity of continuous-time antialiasing filters and alleviating dynamic range requirements of analog-to-digital converters. As a consequence of the structure's low sensitivity to process variations, predicted by theory and verified in the laboratory by measurements on all samples of the same batch, it was possible to apply capacitor arrays having minimum feasible size units of 100 fF to implement the filter coefficients, leading to substantial savings in power consumption. Implemented in a standard 0.8-/spl mu/m CMOS process with poly-poly capacitors, the experimental device samples the incoming continuous-time analog signal at 48 MHz and presents a filtered sampled-data output at 16 MHz, with a measured pass-band deviation smaller than 0.22 dB up to the cutoff frequency of 3.6 MHz, output noise power spectrum of 1.1 nV/sub RMS///spl radic/(Hz) and a signal handling ability of 1.4 V/sub pp/, resulting in a dynamic range of 48 dB, meeting the usual specifications for video-frequency signal processing.     

Compact planar and vialess composite low-pass filters using folded stepped-impedance resonator on liquid-Crystal-polymer substrate

A compact composite low-pass filter, designed by the image parameter method and semilumped component approach, will be described and results for cutoff frequency ranging from C- to V-band will be presented. This composite design combines four filter sections and the presence of a strong attenuation pole near the cutoff frequency provides an extremely sharp attenuation response, while ensuring good matching properties in the passband, making this filter design very attractive for harmonic spurious response suppression or diplexing. The lumped-element schematic of the filter has been implemented using a combination of a stepped-impedance filter and folded stepped-impedance resonators. The overall folded layout has been optimized using full-wave simulation and occupies an ultra-compact area of only 5/spl times/5 mm/sup 2/ for a C-band filter. Measured results exhibit rejection of the attenuated pole greater than 40 dB. Similar filter designs have been realized for C- and V-bands. These filters have been fabricated on a liquid-crystal-polymer substrate demonstrating a high performance, ultra-compact, and very low-cost solution for RF and millimeter-wave applications.     

Narrow passband high-temperature superconducting filters of highly compact sizes for personal communication service applications

A novel highly compact high-temperature superconducting filter based on spiral lumped elements was demonstrated for personal communication system applications. The filter consists of eight-pole microstrip resonators enclosed in a substrate 0.5 /spl times/ 5 /spl times/ 32 mm. The filter was designed to have a bandwidth of 17 MHz and a center frequency of 1760 MHz. A low insertion loss of 0.4 dB in the passband with an out-of-band rejection loss of about -70 dB was observed at 65 K. Measured characteristics of the filter showed good agreement with simulated responses.     

A spur-reduction technique for a 5-GHz frequency synthesizer

A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated for verification in a 0.18-/spl mu/m CMOS process. It exhibits phase noise of -79 and -113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 /spl mu/s.     

A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique

A near-infrared heart-rate measurement IC that processes the photoplethysmographic signal was designed using a 0.35-/spl mu/m CMOS technology. The IC consists of a current-to-voltage (I-V) converter, a buffer, a sample-and-hold circuit, a second-order continuous-time low-pass filter (CT-LPF), a comparator, and a timing circuit that is used to pulse the external light-emitting diode with a very low duty cycle to reduce its power consumption. The current steering technique is employed in the design of the CT-LPF to meet the requirement for very low cutoff frequency. The circuit operates from a 3-V lithium battery, occupies a core area of 0.46 mm/sup 2/ and has a power consumption of 4.5 mW. The measurement results corroborate with simulation results and show that the CT-LPF can achieve a cutoff frequency of as low as 0.25 Hz. This demonstrates the feasibility of current steering technique in the design of filter for low-frequency application.     

Accurate Analysis Equations and Synthesis Technique for Unilateral Finlines

Accurate analysis equations and synthesis techniques are presented for unilateral finlines, valid over a wide range of structural parameters and substrate dielectic constants (1/spl les/epsilon/sub r//spl les/3.75). These expressions are usable for computing the cutoff wavelength to within +-0.6 percent, the guided wavelength to within +-2 percent, and the characteristic impedance (based on the power-voltage definition) to within +-2 percent, of the spectral-domain method, over the normalized frequency range 0.25/spl les/b/lambda/spl les/0.6.