N管开启电压调整主入对P—结击穿电压的影响

为了讨论了问题方便，定义了两种Ｐ－Ｎ：“漏Ｐ－Ｎ结”和“单纯Ｐ－Ｎ结”。分析了二者击穿电压相关因素的差别，认为“漏Ｒ－Ｎ结”击穿电压与沟道区杂质浓度密切相关。ＥＥＰＲＯＭ的研制中，要求“漏Ｐ－Ｎ结”击穿电压≥２０Ｖ，即沟道区杂质浓度要低到一定的程度，而同时又必须保证一定的开启电压，即沟道区杂质浓度要高到一定的程度，通过分析与实验，提出了解决这一矛盾的通用原则。     

EEPROM工艺中场开启电压的特殊要求与对策

ＥＥＰＲＯＭ要求场开启电压≥２０Ｖ，Ｐ－Ｎ结击穿电压也要求≥２０Ｖ，前者需提高场区杂质浓度，而后者则需要降低场杂质浓度，通过工艺模拟和实验找到了一种化解这个矛盾的对策，首先根据Ｐ－Ｎ结击穿电压的要求确定场区杂质浓度，继而大幅度调节场氧厚度，从而使二者都能满足要求。     

提高E^2PROM中NMOS管源漏穿通电压的实验研究

为了提高Ｅ＾２ＰＲＯＭ中Ｎ管源漏穿通电压，用实验的方法对制造工艺进行了研究。结果表明，高能量注入是提高ＶＰＴ的有效手段，但受到ｐｎ结击穿的限制，只适用于低区短沟Ｎ管；ＤＤＤ工艺大幅度高ＶＰＴ，但ｐｎ结击穿电压低于２０Ｖ，不能应用于高压ＭＯＳ管；采用适量的防穿通注入和适当增大沟道长度为最理想的工艺途径。     

采用硅平面工艺制造垂直沟道结型场效应晶体管

采用自对准和掺杂多晶硅技术制造出了一种具有新结构的垂直沟道结型场效应晶体管。因为很多沟道容易集成在单片上,这种结构适用于大功率器件。它也适用于高频器件,因为对于高频工作的两个根本的条件,即足够低的栅电阻和小的沟道长度能很容易地实现。这种器件显示出类似三极管的电流-电压特性,它由沟道杂质浓度和栅极扩散的分布所决定。为音频放大器设计的 n 型沟道,4毫米×4毫米、5520个沟道的功率场效应晶体管的典型特性是:电压放大系数为5;源-栅击穿电压为60伏;漏-栅击穿电压为200伏;在 V_(DS)=7伏时 I_(DSS)=4安。     

高压偏移栅P沟MOSFET的电离辐照性能研究

详细研究了高压偏移栅Ｐ沟ＭＯＳＦＥＴ在Ｃｏ＾６０－γ辐照下击穿电压随辐照剂量的变化关系。结果表明：；击穿电压的辐照剂量响应与漂移区杂质面密度、票移区长度、场板长度以及漏区结构有关。另外，γ辐照志致导通电阻增加。结果证实了我们以前提出的电离辐照引起击穿电压变化的机制。对实验现象给出了比较圆满的解释。结论对研制电离辐射加固高压偏移栅Ｐ沟ＭＯＳＦＥＴ具有重要的指导作用。     

高击穿电压InAIAs／n~＋－InGaAs HFET

高击穿电压ＩｎＡＩＡｓ／ｎ￣＋－ＩｎＧａＡｓＨＦＥＴ最近报道了一种适于高压应用的ＩｎＰ基ＨＦＥＴ，它采用的是双应变外延结构。为了提高器件的击穿电压，采用了如下方法：①采用量子阶沟道，以实现电子的量子化和提高有效沟道的带隙；②使用应变的Ｉｎ＿（０．４１...     

SOI高压MOSFET的电流-电压特性模拟

在不同漂移区浓度分布下 ,通过二维数值模拟充分地研究了薄膜 SOI高压 MOSFET击穿电压的浓度相关性 ,指出了击穿优化对 MOSFET漂移区杂质浓度分布的要求。分析了MOSFET的电场电位分布随漏源电压的变化 ,提出寄生晶体管击穿有使 SOI MOSFET击穿降低的作用。     

高压编移栅P沟MOSFET的电离辐照性能研究

详细研究了高压偏移栅Ｐ沟ＭＯＳＦＥＴ在Ｃｏ６０－γ，辐照下击穿电压随辐照剂量的变化关系．结果表明：击穿电压的辐照剂量响应与漂移区杂质面密度、漂移区长度、场板长度以及漏区结构有关．另外，γ辐照导致导通电阻增加．结果证实了我们以前提出的电离辐照引起击穿电压变化的机制．对实验现象给出了比较圆满的解释．结论对研制电离辐射加固高压偏移栅Ｐ沟ＭＯＳＦＥＴ具有重要的指导作用．     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.     

L、S波段俘越二极管性能参数的实验研究

在以击穿电压V_b和结电咨C_j(-60)作为器件低频参数的基础上,研究了器件低频参数与高频性能的关系,增添电容比C_r(=[C_j(-1)]/[C_j(-60)]作为低频参数.实践表明,L、S波段俘越二极管各有相应的C_r最佳范围,凡具有最佳C_r范围的器件有好的俘越振荡性能.本文还介绍了器件C_r与外延材料的杂质浓度N的关系.可据此关系选抒外延材料的杂质浓度N来制造器件,使得80%以上批次的器件部具有好的俘越振荡性能.     

A geometrical model of the threshold voltage of short and narrow channel MOSFETs

A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program.     

Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET'sand its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi₂ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8×10⁶ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V     

An asymmetrically doped buried-layer (ADB) structure forlow-voltage mixed analog-digital CMOS LSI's

A new CMOS structure has been developed that is distinguished by its asymmetrically doped buried layer (ADB). This structure makes it possible to achieve high drain output resistance and high transconductance necessary for high-performance analog circuits with a low-voltage power supply. The ADB structure has a high-impurity-concentration “pocket” layer near the channel edge of the buried layer only on the source side and a low-impurity surface region through the channel. The source-side channel region determines the threshold voltage and the drain-side channel region absorbs the drain potential. The low-impurity surface region reduces impurity scattering and enables high transconductance. The fabricated ADB CMOS structure increased the drain output resistance, transconductance, and saturation current down to a 0.3-μm channel length, as compared to a control structure. Furthermore, the drain junction capacitance was reduced because of the low impurity concentration beneath the drain region     

漂移区纵向线性掺杂的SOI高压器件研究

随着SOI层厚度的变化,当SOI层的厚度为2μm时,SOI LDMOS器件具有一个最佳的击穿电压.如果漂移区纵向的杂质浓度为线性分布,那么它的纵向电场就会为一个常数,击穿电压会达到最大值,而这种杂质浓度线性分布的漂移区可以通过热扩散得到.采用这种方法制得的SOI LDMOS的纵向击穿电压提高了43%,导通电阻降低了24%,这是因为它的表面浓度更高.     

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping.<>     

薄型双漂移区高压器件新结构的耐压分析

提出与CMOS工艺兼容的薄型双漂移区(TD)高压器件新结构.通过表面注入掺杂浓度较高的N-薄层,形成不同电阻率的双漂移区结构,改变漂移区电流线分布,降低导通电阻;沟道区下方采用P离子注入埋层来减小沟道区等位线曲率,在表面引入新的电场峰,改善横向表面电场分布,提高器件击穿电压.结果表明:TD LDMOS较常规结构击穿电压提高16%,导通电阻下降31%.     

全耗尽SOI LDMOS击穿电压的分析

SOI技术已经成功地应用到功率集成电路中,击穿电压是功率器件一个重要的参数。文章分析了SOI LDMOS的击穿电压与漂移区掺杂浓度的关系,并计算了击穿电压。文中首先定义出漂移区临界掺杂浓度,然后分别给出了实际掺杂浓度高于和低于临界掺杂浓度的击穿电压计算公式。计算结果与文献中给出的数值相吻合,证明了模型的正确性。     

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structuresfor high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V_th lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V_th lowering at 0.4-μm gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4-μm gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4-μm gate length