Study of hybrid orientation structure wafer

Two types of 5μm thick hybrid orientation structure wafers,which were integrated by（110）or（100） orientation silicon wafers as the substrate,have been investigated for 15-40 V voltage ICs and MEMS sensor applications.They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique,and have been presented in China for the first time.The thickness of BOX SiO₂ buried in wafer is 220 nm.It has been found that the quality of hybrid orientation structure with（100）wafer substrate is better than that with（110）wafer substrate by"Sirtl defect etching of HOSW".     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Preparation of silicon-on-gallium arsenide wafers for monolithicoptoelectronic integration

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (≈100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques     

The benefits of bonding: silicon on insulator for bipolar ICs

The use of silicon on insulator (SOI) is currently restricted to MOS integrated circuits. The author describes a research programme aimed at extending the benefits of SOI to bipolar devices. The process uses twin wafers, electrochemically bonded to produce oxide-isolated active regions of high purity and very low defect density     

Low-Temperature Silicon-to-Silicon Anodic Bonding Using Sodium-Rich Glass for MEMS Applications

In the present work, silicon-to-silicon anodic bonding has been accomplished using an intermediate sodium-rich glass layer deposited by a radiofrequency magnetron sputtering process. The bonding was carried out at low direct-current voltage of about 80 V at 365°C. The alkali ion (sodium) concentration in the deposited film, the surface roughness of the film, and the flatness of the silicon wafers were studied in detail and closely monitored to improve the bond strength of the bonded silicon wafers. The effect of chemical mechanical polishing (CMP) on the surface roughness of the deposited film was also investigated. The average roughness of the deposited film was found to be ~6 Å, being reduced to 2 Å after CMP. It was observed that the concentration of sodium ions in the deposited film varied significantly with the sputtering parameters. Scanning electron microscopy was used to obtain cross-sectional images of the bonded pair. The bonding energy of the bonded wafer pair was measured using the crack-opening method. The bonding energy was found to vary from 0.3 J/m² to 2.1 J/m² for different bonding conditions. To demonstrate the application of the process developed, a sealed cavity was created using the silicon-to-silicon anodic bonding technique, which can be used for fabrication of devices such as capacitive pressure sensors and Fabry– Perot-based pressure sensors. Also, a matrix of microwells was fabricated using this technique, which can be used in various biomicroelectromechanical system applications.     

Low temperature glass-to-glass wafer bonding

In this paper, results of successful anodic bonding between glass wafers at low temperature are reported. Prior to bonding, a special technique was used, i.e., an amorphous and hydrogen free silicon film was deposited on one of the glass wafers using a sputtering technique. The effects of bonding temperature and voltage were investigated. The bonding temperature and the voltage applied ranged from 200/spl deg/C to 300/spl deg/C and 200 V to 1000 V, respectively. As the bonding temperature and bonding voltage increased, both the unbonded area and the size of voids decreased. Scanning electron microscope (SEM) observations show that the two glass wafers are tightly bonded. The bond strength is higher than 10 MPa for all the bonding conditions. Furthermore, the bond strength increases with increasing bonding temperature and voltage. The study indicates that high temperature and voltage cause more Na/sup +/ ions to neutralize at the negative electrode, which leads to higher charge density inside the glass wafer. Furthermore, the transition period to the equilibrium state also becomes shorter. It is concluded that the anodic bonding mechanisms involve both oxidation of silicon film and the hydrogen bonding between hydroxyl groups.     

用于先进 CMOS电路的 150 mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mmP/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mmP/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

薄膜SOI上大于600 V LDMOS器件的研制

针对600 V以上SOI高压器件的研制需要,分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案,并通过仿真预言其可行性。在埋氧层为3μm,顶层硅为1.5μm的注氧键合(Simbond)SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场,设计了具有线性渐变掺杂60μm漂移区的LDMOS结构。为提高纵向耐压,利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明,器件关态击穿电压可达600 V以上(实测832 V),开态特性正常,阈值电压提取为1.9 V,计算开态电阻为50Ω.mm2。     

Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film

A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices.     

Integrated circuit design for physical unclonable function using differential amplifiers

A physical unclonable function (PUF) based on process variations on silicon wafers is a very promising technology which finds various applications in identification and authentication, but only a few integrated circuits have been reported so far. As those circuits are vulnerable to power supply noises, switching noises and environmental variations, they lead to a reliability issue such as time-varying or metastable responses. To resolve this issue, this letter proposes a new integrated circuit design for PUFs using differential amplifiers. The feasibility of the proposed circuit has been theoretically analyzed and validated through HSPICE simulations for the previous and proposed circuits.     

Using Transmission Laser Bonding Technique for Line Bonding in Microsystem Packaging

The transmission laser bonding (TLB) technique has been developed for the formation of continuous line bonds for microsystem packaging applications. Line bonds are generated by overlapping single bonding spots, in which the degree of overlapping is achieved by varying the scanning speed of the laser as it irradiates the bonding wafers. An analytical model has been developed to guide the TLB process, attaining a uniform laser intensity that produces uniform bonds, satisfying the bonding requirements. Guided by this model, experiments have been conducted to bond Pyrex glass-to-Si wafers at various bonding conditions. To demonstrate the reliability of the technique and the model developed, the strength of the resulting bonded pairs has been evaluated by a micro tensile tester. At contact pressures higher than 1 MPa, the strength of bonded lines can reach a stable value of 9.2 MPa, which is comparable to those obtained by other major bonding processes. To further understand the associated bonding mechanism, the bonded interface has also been analyzed using auger electron spectroscopy and X-ray photoelectron spectroscopy, quantifying the drifting or diffusion of atoms that occurs between glass and Si wafers during the bonding process     

Selective bonding and encapsulation for wafer-level vacuum packaging of MEMS and related micro systems

A laser-assisted bonding technique is demonstrated for low temperature region selective processing. A continuous wave carbon dioxide (CO₂) laser (λ=10.6 μm) is used for solder (Pb37/Sn63) bonding of metallized silicon substrates (chips or wafers) for MEMS applications. Laser-assisted selective heating of silicon led to the reflow of an electroplated, or screen-printed, intermediate solder layer which produced silicon–solder–silicon joints. The bonding process was performed on fixtures in a vacuum chamber at an air pressure of 10⁻³ Torr to achieve fluxless soldering and vacuum encapsulation. The bonding temperature at the sealing ring was controlled to be close to the reflow temperature of the solder. Pull test results showed that the joint was sufficiently strong. Helium leak testing showed that the leak rate of the package met the requirements of MIL-STD-883E under optimized bonding conditions and bonded packages survived thermal shock testing. The testing, based on a design of experiments method, indicated that both laser incident power and scribe velocity significantly influenced bonding results. This novel method is especially suitable for encapsulation and vacuum packaging of chips or wafers containing MEMS and other micro devices with low temperature budgets, where managing stress distribution is important. Further, released and encapsulated devices on the sealed wafers can be diced without damaging the MEMS devices at wafer level.     

Surface-related phenomena in the direct bonding of silicon and fused-silica wafer pairs

Direct bonding is the result of a complex interaction between chemical, physical and mechanical properties of the surfaces to be bonded and is therefore strongly correlated with the surface state of the materials. Phenomena characteristic of the actual bonding process are (a) the formation of an initial bond area, (b) bond energy, and (c) bond-front velocity. The effects of variations in surface state on these process characteristics have been investigated for silicon, oxidized silicon and fused-silica wafer pairs. The surface bond energy of hydrophilic wafers is in the range of 0.05–0.2 J/m² and is largely determined by the hydrogen bonds formed. The bond energy of hydrophobic wafers is a factor of 10 smaller and is determined by Van der Waals attractive forces. The bond-front velocity is determined by the surface state and the stiffness of the wafer. Both bond energy and bond-front velocity show ageing effects.     

硅/硅直接键合的界面应力

硅/硅直接键合技术广泛应用于SOI,MEMS和电力电子器件等领域,键合应力对键合的成功和器件的性能产生很大的影响。键合过程引入的应力主要是室温下两硅片面贴合时表面的起伏引起的弹性应力;高温退火阶段由于两个硅片的热膨胀系数不同引起的热应力和由于界面的本征氧化层或与二氧化硅键合时二氧化硅发生粘滞流动引起的粘滞应力。另外,键合界面的气泡、微粒和带图形的硅片键合都会引入附加的应力。     

DeleCut: Producing High-Quality SOI Structures by Hydrogen Ion Implantation

DeleCut, a new technology for producing SOI structures, is presented [1]. It is an improvement on the SmartCut^® process. DeleCut allows one to reduce annealing temperature and offers a lower concentration of radiation defects, a thinner transferred silicon layer, and a thinner transition layer between the silicon and the insulator (oxide). This process technology makes it possible to obtain silicon and insulator layers whose thicknesses are uniform within a few nanometers. A batch of SOI wafers of diameter 100–150 mm is fabricated with a pilot production line, the silicon films being free from dislocations. On the basis of the SOI structures, several types of submicrometer test CMOS circuits are successfully produced.     

CMOS-SOI platform for monolithic integration of crystalline silicon MEMS

A new platform for the fabrication of crystalline micro- and nano-electromechanical systems fully integrable with CMOS is presented. A pre-CMOS process on SOI wafers allows bulk silicon areas for standard CMOS processing and areas with a stack layer of silicon and silicon oxide to be obtained, in which a set of microelectromechanical devices can be fabricated. An integrated resonant beam system with electrical actuation and detection fabricated according to the presented approach is provided.     

Plasma immersion ion implantation for SOI synthesis: SIMOX and ion-cut

We have demonstrated feasibility to form silicon-on-insulator (SOI) substrates using plasma immersion ion implantation (PIII) for both separation by implantation of oxygen and ion-cut. This high throughput technique can substantially lower the high cost of SOI substrates due to the simpler implanter design as well as ease of maintenance. For separation by plasma implantation of oxygen wafers, secondary ion mass spectrometry analysis and cross-sectional transmission electron micrographs show continuous buried oxide formation under a single-crystal silicon overlayer with sharp Si/SiO₂ interfaces after oxygen plasma implantation and high-temperature (1300°C) annealing. Ion-cut SOI wafer fabrication technique is implemented for the first time using PIII. The hydrogen plasma can be optimized so that only one ion species is dominant in concentration and there are minimal effects by other residual ions on the ion-cut process. The physical mechanism of hydrogen induced silicon surface layer cleavage has been investigated. An ideal gas law model of the microcavity internal pressure combined with a two-dimensional finite element fracture mechanics model is used to approximate the fracture driving force which is sufficient to overcome the silicon fracture resistance.     

多线切割加工中单晶硅片晶向影响关系研究

单晶硅片的晶向是大规模集成电路衬底材料的一个重要参数。硅片的晶向是根据单晶的生长晶向以一定的角度粘结固定到多线切割机的工作台上切割实现的。但是在实际粘结操作过程中,单晶棒易滑移导致角度产生偏差从而影响到加工后的硅片晶向超差而报废。为了明确粘结角度偏差对切割后硅片晶向的影响关系,在产生误差的情况下做出科学正确的判断,对粘结角度的计算原理进行了推导、得出了单晶棒X．ray定向仪的计算原理。在此基础上,对粘结产生的角度误差对晶向的影响关系进行了理论推导．得出了它们之间的明确影响关系的函数关系。此函数关系表明。粘结过程的角度误差对硅片晶向的影响是复杂的反三角函数关系,必须通过实际计算才能确定其大小。通过此函数关系,可以明确的确定单晶棒粘结的角度偏差对硅片晶向的影响。为科学的现场判断提供了理论依据,能有效的服务于生产实际,．