共查询到20条相似文献,搜索用时 15 毫秒
1.
Hamamoto T. Furutani K. Kubo T. Kawasaki S. Iga H. Kono T. Konishi Y. Yoshihara T. 《Solid-State Circuits, IEEE Journal of》2004,39(1):194-206
This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-/spl mu/m DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified. 相似文献
2.
Kondoh H. Notani H. Yamanaka H. Higashitani K. Saito H. Hayashi I. Kohama S. Matsuda Y. Oshima K. Nakaya M. 《Solid-State Circuits, IEEE Journal of》1993,28(7):808-815
An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing 相似文献
3.
Kye-Hyun Kyung Hi-Choon Lee Ki-Whan Song Ho-Sung Song Keewook Jung Joon-Seo Moon Byoung-Sul Kim Sung-Burn Cho Changhyun Kim Soo-In Cho 《Solid-State Circuits, IEEE Journal of》2001,36(5):735-743
A 2.5-V 288-Mb packet-based DRAM with 32 banks and 18-DQ organization architecture achieving a peak bandwidth of 2.0-GB/s at V DD=2.25 V and T=100°C has been developed using (1) an area- and performance-efficient chip architecture with a mixture of high-speed interface circuits with DRAM peripheral circuits to increase cell efficiency; (2) a multilevel controlled bitline equalizing scheme and a distributed sense amplifier driving scheme to enhance DRAM core timing margin while increasing the number of cells per wordline for cell efficiency over the previous subwordline driving scheme; (3) a flexible column redundancy scheme with multiple fuse boxes instead of excessive spare memory cell arrays for 143 internal I/O architecture; and (4) optimized I/O circuits and pin parasitic design including pad and package to maximize the operating frequency 相似文献
4.
Weston H.T. Banu M. Fang S.-C. Diodato P.W. Stanik T.D. Wilford P.A. Hsu F.M. 《Solid-State Circuits, IEEE Journal of》1992,27(7):1041-1049
The development of a low-power 12-channel multiplexer-demultiplexer pair that is clocked at the standard synchronous optical network (SONET) rate of 622.08 MHz is discussed. Each device has been integrated in silicon using a 0.75- mu m NMOS VLSI technology that provides high fabrication yield at relatively low cost. Highlighted are the analog interface circuits of the two chips. These include a phase splitter and amplifier for the maser clock input, a precision 50- Omega output driver for high-speed synchronous-transport-signal-12 (STS-12) data, as well as input amplifier and an output stage for low-speed differential STS-1 data.<> 相似文献
5.
A 640-Mb/s 2048-bit programmable LDPC decoder chip 总被引:3,自引:0,他引:3
A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-/spl mu/m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW. 相似文献
6.
7.
《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1973,61(10):1504-1505
An optical-repeater error-rate experiment is described in which the carrier generator is a directly modulated double heterojunction GaAs laser. It is shown that 274-Mb/s modulation can be achieved with sufficiently high quality that the received signal can be regenerated with error rates in accordance with predictions based on receiver thermal noise. 相似文献
8.
Engling Yeo Augsburger S.A. Davis W.R. Nikolic B. 《Solid-State Circuits, IEEE Journal of》2003,38(7):1234-1241
Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-/spl mu/m CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm/sup 2/ chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit. 相似文献
9.
This paper describes a new sigma-delta (Σ-Δ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK/GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), Σ-Δ modulator, and automatic calibration circuit, has been implemented in a 0.6-μm BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK 相似文献
10.
A multihighway serial/parallel (S/P) converted LSI chip suitable for the broadband Integrated Services Digital Network (B-ISDN) node interface is presented. The chip, fabricated with 0.8-μm BiCMOS technology, handles 32-highway×8 b of S/P, P/S conversion at up to 250 Mb/s and has a power dissipation of 700 mW. The chip features cross-access memory and a current-cut-type CMOS/ECL interface circuit. Each of these features is described and evaluated. A newly developed BiNMOS-type D-flip-flop (D-FF) is used to speed up the cross-access memory and is compared to a CMOS D-FF 相似文献
11.
Brigati S. Colombara P. D'Ascoli L. Gatti U. Kerekes T. Malcovati P. 《Solid-State Circuits, IEEE Journal of》2002,37(7):887-894
In this paper, we present an integrated 155-Mb/s burst-mode receiver (BMR) for passive optical network (PON) applications. The chip has been designed to receive optical signals over a wide dynamic range (-30 to -8 dBm) and temperature range (-40°C to +85°C). The chip was implemented using a 0.8-μm 35-GHz SiGe BiCMOS technology and occupies an area of 4.3×4.9 mm2 with a power consumption of 500 mW from a supply voltage of 5 V (3.3 V for the digital PECL output). In the receiver analog front end, we used a low-noise wide-band transimpedance amplifier followed by a nonlinear gain stage to cover a wide signal range without changing the transimpedance gain. The circuit dynamically adjusts the receiver threshold voltage through a feedback loop, thus optimizing the pulsewidth distortion and canceling the optical as well as the electrical offset voltages 相似文献
12.
Shiratake S. Miyakawa T. Takeuchi Y. Ogiwara R. Kamoshida M. Hoya K. Oikawa K. Ozaki T. Kunishima I. Yamakawa K. Sugimoto S. Takashima D. Joachim H.-O. Rehm N. Wohlfahrt J. Nagel N. Beitel G. Jacob M. Roehr T. 《Solid-State Circuits, IEEE Journal of》2003,38(11):1911-1919
This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-/spl mu/m three-metal CMOS technology. A small die size of 96 mm/sup 2/ and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 /spl mu/m/sup 2/, which is smaller than a 0.13-/spl mu/m SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 /spl mu/A. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/. 相似文献
13.
A 156-Mb/s CMOS optical receiver for burst-mode transmission 总被引:1,自引:0,他引:1
In a point-to-multipoint fiber-optic subscriber system using TDMA (time division multiple access), the receiver should be able to handle burst-data packets with different amplitudes, Moreover, high-bit-rate operation is desired for multimedia communications. The operational speed is mainly restricted by the input parasitic capacitance of the preamplifier. Reducing the input impedance of the preamplifier widens its frequency bandwidth, and it makes high-speed operation possible. A multistaged preamplifier using feedforward phase compensation technique has been devised for small input impedance with stable operation at high frequency. Multistaged feedforward bias control is used for quick response to burst data, and the time constant is also reduced for high-speed operation. Using these design techniques, an optical receiver IC was fabricated using standard 0.5-μm CMOS technology. The instantaneous response receiver has high sensitivity of -35.6 dBm, a wide dynamic range of more than 26 dB for burst-mode optical input at 156 Mb/s, and requires no external adjustment. The use of standard CMOS technology and the freedom from external adjustment make it possible to build an inexpensive receiver module 相似文献
14.
《IEEE transactions on circuits and systems. I, Regular papers》2009,56(5):1017-1029
15.
A CMOS line driver for high-speed data communication according to the T1 and CEPT recommendations is presented. The differential output swing is 7.2 V pp on a load of 22.8 Ω from a single 5-V supply. A novel quiescent current control scheme is used. The driver occupies an area of 6.5 mm2 using a 2-μm p-well CMOS technology 相似文献
16.
Wei-Hung Chen Guang-Kaai Dehang Jong-Woei Chen Shen-Iuan Liu 《Solid-State Circuits, IEEE Journal of》2001,36(10):1498-1505
In this paper, a serial link for AS-memory systems fabricated in a 0.25-μm standard CMOS technology is presented. This serial link utilizes a pulsewidth modulation (PWM) technique. By transmitting the PWM-encoded signal with periodic rising edges, the clock can be implicitly embedded in the data stream and the associating overhead needed in clock/data recovery circuits can, be mitigated. The symbol rate is 200 Mb/s and the equivalent data rate is 400 Mb/s. The PWM transceiver dissipates 66.5 mW at a 2.5-V supply voltage. It is suitable for the AS-memory systems in which the pin count is limited and elaborate clock/data recovery circuits are not required 相似文献
17.
Muljono H. Beom-Taek Lee Yanmei Tian Yanbin Wang Atha M. Huang T. Adachi M. Rusu S. 《Solid-State Circuits, IEEE Journal of》2003,38(11):1846-1856
This paper describes the design of a system bus interface for the 130-nm Itanium/sup /spl reg//2 processor that operates at 400MT/s (1 megatransfer = 1 Mb/s/pin) with a peak bandwidth of 6.4 GB/s. The high-speed operation is achieved by employing source-synchronous transfer with differential strobes. Short flight time is accomplished by double-sided placement of the processors. Preboost and postboost edge-rate control enables fast clock-to-output timing with tight edge-rate range. The built-in input/output (I/O) loopback test feature enables I/O parameters to be tested on die, using a delay-locked loop and interpolator with 21-ps phase-skew error and 15-ps rms jitter. Power modeling methodology facilitates accurate prediction of system performance. 相似文献
18.
Yoshimura T. Kondoh H. Matsuda Y. Sumi T. 《Solid-State Circuits, IEEE Journal of》1996,31(7):1063-1066
A compact 622-Mb/s/port bit/frame synchronizer is presented. Sampling equally-phased clocks from a phase-locked loop (PLL) at the data transition edges, the bit synchronizer selects the optimum one as the extracted clock. An elastic serial-to-parallel converter is used for the frame synchronization. The circuit is designed for a 32-port ATM switch chip, achieving 622-Mb/s port capacity by four parallel 156-Mb/s bits. Using 0.5-μm CMOS technology, the circuit was verified by simulations. The bit synchronizer consumes only 15 mW under typical conditions 相似文献
19.
Bree M.A. Dodds D.E. Bolton R.J. Kumar S. Daku B.L.F. 《Solid-State Circuits, IEEE Journal of》1992,27(2):184-190
A node-parallel Viterbi decoding architecture and bit-serial processing and communication are presented. An important aspect of this structure is that short-constraint-length decoders may be interconnected, without loss of throughput, to implement a Viterbi decoder of larger constraint length. The convolutional encoder trellis is modeled by appropriate wiring of decoder processing nodes: a variety of generating codes can be accommodated. Bit-serial communication links between nodes require only a single wire each and thus interconnection area is relatively small. During each decoding cycle, more than 50 b need to be communicated on each serial link and thus the technique is limited to moderate bit rate applications. A constraint length K=4 `proof of concept' chip was developed using 9860 transistors in 3 μm CMOS on a 4.51-mm×4.51-mm die size. The complete circuit operates at 280 kb/s and supports any rate 1/2 or 1/3 code with eight-level soft decision 相似文献
20.
A CMOS operational amplifier (OPAMP) for use as a line driver for high-speed T1/E1 data communication link is described. The differential output swing, using a single 3.3-V power supply, is 5.2-V peak-to-peak on a 20-/spl Omega/ load. Novel circuits are used to control the closed-loop output impedance, quiescent bias current, and frequency compensation to ensure stable operation over varying temperature and load conditions. A special circuitry tristates the output in case of power-supply failure. The OPAMP achieves a unity-gain bandwidth of 35 MHz with only 10 mA of quiescent current. A new output-current-sense circuitry is used to provide a current feedback to adjust the output impedance for proper line termination as well as to provide short-circuit protection from excessive output currents. Using 0.35-/spl mu/m n-well CMOS technology, the amplifier occupies 0.69 mm/sup 2/ of area. 相似文献