Asynchronous gate-diffusion-input (GDI) circuits

Novel gate-diffusion input (GDI) circuits are applied to asynchronous design. A variety of GDI implementations are compared with typical CMOS asynchronous circuits. Dynamic GDI state holding elements are 2/spl times/ smaller than CMOS C-elements, 30% faster, and consume 85% less power, but certain CMOS elements are preferred when static storage is called for. A GDI bundled controller outperforms CMOS on all accounts, having 1/3 the delay and requiring less than half the area while consuming the same power. A combination CMOS-GDI circuit provides the optimal solution for qDI combinational logic, saving 1/3 the power, half the area, and 10% in delay relative to a CMOS implementation. GDI circuits also provide some measure of enhanced hazard tolerance.     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

Technology mapping for high-performance static CMOS and passtransistor logic designs

Two new techniques for mapping circuits are proposed in this paper. The first method, called the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the static CMOS/pass transistor logic (PTL) method, uses a mix of static CMOS and PTL to realize the circuit and utilizes the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all of the ISCAS'85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on different libraries shows an average delay reduction above 18% for OTR, and an average delay reduction above 35% for the static CMOS/PTL method, with significant savings in the area     

Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%.      

On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.     

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.     

A novel high-speed CMOS circuit based on a gang of capacitors

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with V_DD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.     

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power–delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power–delay performance of these two topologies is proposed.      

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment

This brief presents a logic synthesis flow that depends on the popular Synopsys Design Compiler to perform logic translation and minimization based on the standard cell library with both pass transistor logic (PTL) and CMOS logic cells. The hybrid PTL/CMOS logic synthesis can generate appropriate circuits considering various design constraints. The proposed multilevel PTL logic cells are automatically constructed from only a few basic cells. Postlayout simulations with UMC 90-nm technology are presented based on the standard cell library with pure PTL, pure CMOS, or hybrid PTL/CMOS cells. Experimental results show that, in most cases, pure PTL circuits have smaller area and power, whereas CMOS circuits, in general, have smaller delay.      

Wave steering to integrate logic and physical syntheses

Wave steering is a unified logic and physical synthesis scheme that algorithmically generates high-throughput circuits with fast turn-around times. Binary decision diagram (BDD)-type structures are altered to satisfy certain electrical constraints, embedded in silicon with pass transistor logic (PTL), and pipelined to very fine granularity using a novel two-phase clocking scheme. This direct PTL mapping of a logic representation provides good electrical estimations to a front-end tool like the logic synthesizer at an early phase of the design cycle. We apply our wave steering technique to high throughput computation-intensive datapath combinational circuits. We achieve an average speedup of 4.2 times compared to standard cell (SC) implementations of high performance arithmetic circuits at the cost of only about 76% average increase in area. The results look extremely encouraging; all the more so, considering that we also achieve an average reduction of 27% in latency and 15% in power compared to SC circuits.     

Performance of CMOS differential circuits

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique     

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

Complex 3D CMOS circuits based on a triple-decker cell

Presents circuit design for a three-dimensional (3D) CMOS integrated process. This process, with its three stacked transistor channels, leads to the very efficient basic circuits: inverter, selector, and NAND2. These elements are used to build a complete cell library with standard elements like NORs, latches, flip-flops, etc. Special macro blocks such as multipliers, SRAMs and content addressable memories (CAMs) complete the circuit library. Novel concepts and implementations of three-dimensional prefabricated semicustom arrays are introduced. These are the NAND array and the selector array, for which technology-dependent logic synthesis is investigated. Area requirements for static 3-D CMOS logic ranges from 50% down to 33% compared to two-dimensional (2-D) CMOS. These figures include the wiring and are caused by the transistor stacking and the large number of interconnection layers used in the 3D CMOS process.<>     

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

In this paper, a new leading-zero counter (or detector) is presented. New boolean relations for the bits of the leading-zero count are derived that allow their computation to be performed using standard carry-lookahead techniques. Using the proposed approach various design choices can be explored and different circuit topologies can be derived for the design of the leading-zero counting unit. The new circuits can be efficiently implemented either in static or in dynamic logic and require significantly less energy per operation compared to the already known architectures. The integration of the proposed leading-zero counter with the leading-zero anticipation logic is analyzed and the most efficient combination is identified. Finally, a simple yet efficient technique for handling the error of the leading-zero anticipation logic is also presented. The energy-delay behavior of the proposed circuits has been investigated using static and dynamic CMOS implementations in a 130-nm CMOS technology.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.     

A novel current controlled configurable RO PUF with improved security metrics

Physical Unclonable Functions (PUFs) are promising hardware security primitives which produce unique signatures. Out of several delay based PUF circuits, Configurable Ring Oscillator (CRO) PUF has got higher uniqueness and it is resilient against modelling attacks. In this paper, we present a novel Current controlled CRO (C-CRO) PUF in which inverters of RO uses different logic styles: static CMOS and Feedthrough logic (FTL). Use of different logic styles facilitates improvement of security metrics of PUF. The analysis of security metrics of the proposed architecture is carried out in 90 nm CMOS technology shows, using FTL logic leads to better security metrics. Proposed C-CRO PUF is also both power and area efficient. Further, in order to measure the vulnerability of proposed PUF, machine learning attack is carried out and the result shows FTL RO based C-CRO PUF is highly resilient to machine learning attack because of its non-linearity property.     

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

Design for concurrent error detection and testability instorage/logic arrays

Storage/Logic Arrays (SLA's) represent a structured logic array approach to the design of VLSI sequential logic. Design for concurrent error detection and testability is complicated in these arrays by the presence of embedded memory elements and multiple levels of logic. A means of designing SLA's for ease of testability and concurrent error detection (CED) is provided in this paper. Test sets for static and dynamic CMOS circuits are described. Fault and error coverage is presented and performance and area costs are analyzed for example circuits. In addition, a means of implementing dynamic CMOS SLA's is presented and shown superior to previous NMOS, static CMOS, and dynamic CMOS approaches based upon power consumption and simplicity of design     

Evaluation of two-summand adders implemented in ECDL CMOSdifferential logic

Four different adders were implemented using a CMOS differential logic, enable/disable differential CMOS logic (ECDL). The authors discuss the design and implementation of several common addition algorithms using ECDL. These adders have the self-timed characteristic. Comparisons are made among these algorithms in terms of delay and area. The actual implementation was done with MOSIS 3-μm scalable process. Evaluations are performed in terms of area and delay. One conclusion that can be made is that the carry-skip adder seems to have the best speed/area combined performance. A first-order modeling method is used to estimate the area and speed of different implementations