低成本BIST映射电路的设计与优化

低成本BIST利用映射电路对自测试线形反馈移位寄存器进行优化,将对故障覆盖率无贡献的测试向量屏蔽掉,有效提高了故障覆盖率,降低了测试功耗。映射电路的设计是低成本BIST设计的关键,为了降低其硬件开销和功耗、提高参数性能,该映射逻辑电路对测试向量的种子进行映射,并通过相容逻辑变量合并、布尔代数化简等方法对映射电路进行优化,有效地降低了测试应用时间、测试功耗和硬件开销。     

基于PSA的高级测试综合

提出了一种基于PSA（多项式符号代数）的高级测试综合方法。首先得到基于多项式符号代数的电路描述，然后通过可测性插入技术，得到电路的可测结构表示；通过可测性分析，提出一种基于多项式符号代数的集成的调度和分配方法，直至获得最终的电路网表。该算法可以减少测试时间和硬件消耗，而且故障的覆盖率也得到提高。实验结果证实了该方法的有效性。     

新型IDDT测试的BIST测试生成器设计

内建自测试(BIST)是一种有效降低测试开销的技术,在瞬态电流测试中得到了应用。本文给出了一种新型的瞬态电流测试BIST测试生成器设计方案,该设计可以产生所需要的测试向量对,同时具有硬件开销小的优点。     

基于March C＋算法的SRAMBIST设计

为了增加存储器测试的可控性和可观测性,减少存储器测试的时间和成本开销,在此针对LEON处理器中的32位宽的SRAM进行BIST设计。采用MarchC＋算法,讨论了SRAM的故障模型及BIST的实现。设计的BIST电路可以与系统很好的相连,并且仅增加很少的输入／输出端口。仿真结果证明,BIST的电路的加入在不影响面积开销的同时,能够达到很好的故障覆盖率。     

内建自测试的测试生成方法研究

内建自测试（BIST）方法是目前可测试性设计（DFT）中应用前景最好的一种方法,其中测试生成是关系BIST性能好坏的一个重要方面。测试生成的目的在于生成尽可能少的测试向量并用以获得足够高的故障覆盖率,同时使得用于测试的硬件电路面积开销尽可能低、测试时间尽可能短。内建自测试的测试生成方法有多种,文中即对这些方法进行了简单介绍和对比研究,分析了各自的优缺点,并在此基础上探讨了BIST面临的主要问题及发展方向。     

用于SOC测试的一种有效的BIST方法

为了提高SOC芯片的可测性和可靠性,我们提出了一种SOC测试的BIST技术的实现方案.针对某所自行研制的数字模拟混合信号SOC芯片,我们使用了不同的可测性技术.比如对模拟模块使用改进的BIST方法,对嵌入式存储器使用了MBIST技术.一系列的测试实验数据表明,该BIST方法能有效提高测试覆盖率.     

基于LFSR优化的BIST低功耗设计

在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗。在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求。     

基于LFSR优化的BIST低功耗设计

在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗.在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求.     

BiCMOS电路可测性设计探讨

本文提出了ＢｉＣＭＯＳ电路的实用可测性设计方案，该方法与传统方法相比，可测性高，硬件花费小，仅需额外添加一个ＭＯＳ管和两个控制端，就可有效地用单个测试码测出ＢｉＣＭＯＳ电路的开路故障和短路故障，减少了测试生成时间，可广泛应用于集成电路设计中。     

实用BiCMOS电路可测性设计

本文提出了ＢｉＣＭＯＳ电路的实用可测性设计方案，该方案与传统方法相比，可测性高，硬件花费小，仅需额外添加两个ＭＯＳ管和控制端，就可有效地用单个测试码测出ＢｉＣＭＯＳ电路的开路故障和短路故障，减少了测试生成时间，可广泛应用于集成电路设计中。     

Integrating testability with design space exploration

Built-in self-test (BIST) has emerged as a promising test solution for high-speed, deep sub-micron VLSI circuits. Traditionally, the testability insertion phase comes after functional logic synthesis and verification in the design cycle. This creates two separate optimisation processes: functional optimisation followed by BIST insertion and optimisation. The first deals with functional design behaviour, while the second deals with test behaviour. Considering testability at such a late stage in the design flow limits efficient design space exploration. In this paper, we consider testability as a design objective alongside area and delay. We extend the concept of design space to include testability and show how this enhanced design space can be used by a high-level synthesis tool. We demonstrate that by taking testability into account at an early stage, we can generate better designs than by leaving BIST insertion to the end of the design cycle.     

Datapath BIST Insertion Using Pre-Characterized Area and Testability Data

There are several ways to insert Built-in Self-Test (BIST) circuitry on a circuit, each of them with particular consequences on area overhead, test application time and fault coverage. This paper presents a BIST insertion methodology applied to datapaths described at the RTL level that uses a database containing: (a) testability data of several types of test pattern generators (TPGs) and signature analyzers (SAs) when connected to several types of functional units and (b) area overhead due to the implementation by a datapath register of each type of those test resources. The availability of this database makes then possible to choose the best test resource types associated to each functional unit in a datapath, leading to good testability and area results.     

Cost/Quality Trade-off in Synthesis for BIST

This paper details our allocation for Built-in Self Test (BIST) technique used by the core part of our Testability Allocation and Control System (TACOS) called IDAT. IDAT tool objective is to fulfill the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the final testable circuit. The allocation process of BIST resources in the data-path is driven by two trade-off techniques performed in order to: (1) at the local level, select the optimal set of Functional Units (FUs) to be BISTed, using a new testability analysis method and (2) at the global level, for each selected FU of this set, choose either to allocate its BIST version (when available in a library) or to connect it to an internal Test Pattern Generator (TPG) and Test Results Checker (TRC). When necessary, a last step of the process is the allocation of scan chains used to test the remaining untested interconnections. Experiments show the results of our allocation for BIST technique on three benchmarks.     

Design for Testability Techniques at the Behavioral and Register-Transfer Levels

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.     

Integration of algorithmic VLSI synthesis with testabilityincorporation

A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary-tree data structure is used throughout the testable design search. Its bottom-up and top-down algorithms provide data-path allocation, constraint estimation, and feedback for design exploration. The partitioning and two-dimensional characteristics of the binary-tree structure provide VLSI design floorplans and global information for test incorporation. A differential equation and elliptical wave filter example were used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple-chain scan paths and BIST (built-in self-test) with different test schedules were explored. Design scores comprised of area, delay, fault coverage, and test time were computed and graphed     

Testability Trade-Offs for BIST Data Paths

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation.     

一种新型低峰值功耗的BIST设计研究

随着手持设备的兴起和芯片对晶片测试的要求越来越高,内建自测试的功耗问题引起了越来越多人的关注。文章对目前内建自测试的可测性设计技术进行了分析,并提出了折叠种子优化降低节点峰值功耗的模型,通过调整种子结构和测试向量的相关性的办法来避免过高的SoC测试峰值功耗。采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用,使得测试时测试向量的输入跳变显著降低,从而大幅度降低节点的峰值功耗。实验结果表明,该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

Integration of partial scan and built-in self-test

Partial-Scan based Built-In Self-Test (PSBIST) is a versatile Design for Testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. PSBIST builds its BIST capability on top a partial scan structure by adding a test pattern generator, an output data compactor, and a PSBIST controller in a way similar to that of deriving a full scan BIST from a full scan structure. However, to make the scheme effective, there is a minimum requirement regarding which flip-flops in the circuit should be replaced by scan flip-flops and/or initialization flip-flops. In addition, test arents are usually added to boost the fault coverage to the range of 95 to 100 percent. These test points are selected based on a novel probabilistic testability measure, which can be computed extremely fast for a special class of circuits. This ciass of circuits is precisely the type of circuits that we obtain after replacing some of the flip-flops.withscan and/or initilization flip-flops. The testability measure is also used for a very useful quick estimation of the fault coverage right after the selection of sean flip-flops, even before the circuit is modified to incorporate PSBIST capability. While PSBIST provides all the benefits of BIST, it incurs lower area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage.     

Estimation of BIST Resources During High-Level Synthesis

Lower bound estimations of functional resources at various stages of high-level synthesis have been developed to guide synthesis algorithms toward optimal solutions. In this paper we present lower bounds on the number of test resources (i.e., registers that generate pseudo-random test patterns and/or compress test responses) required to test a synthesized data path using built-in self-test (BIST). The bounds on different types of test resources are proved to be individually achievable and experiments show that in most cases the bounds can be achieved simultaneously and with minimum number of functional registers. Efficient ways of computing the lower bounds are developed. The estimations are performed on scheduled data flow graphs with a given module assignment and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of BIST resources to test itself.     

Behavioral Testability Insertion for Datapath/Controller Circuits

A method for test synthesis in the behavioral domain is described.The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This testbehavior describes the behavior of the design in test mode. Thenormal-mode design behavior and test-mode test behavior are combinedand then synthesized by any general-purpose synthesis system toproduce a testable design with inserted BIST structures. The testbehavior is derived from the design behavior using testabilityanalysis based on metrics that quantify the testability of signalsand variables embedded within behaviors. The insertion method iscombined with a behavioral test scheme thatintegrates a) the design controller and test controller, b) testingof the entire datapath and controller. Examples show that when thetestability insertion procedure is used to modify a behavior beforesynthesis, the resulting synthesized physical implementation isindeed more easily tested than an implementation synthesized directlyfrom the original behavior.