能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTLPLA与普通结构的PLA相比,包括功率时钟电路的     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTL PLA与普通结构的PLA相比,包括功率时钟电路的功耗在内,ERTL PLA仍节省65%～77%的功耗.     

An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits

This paper analyzes the timing jitter accumulation which is produced in a chain of regenerative repeaters when a second-order phase-locked loop (PLL) is used as a timing filter. In a PLL timing recovery circuit, the growth of timing jitter varies with the value of damping factorzeta. In this paper, therefore, approximate equations of timing jitter accumulation are given with respect to a case in whichzetais sufficiently large, and the timing jitter is calculated with a digital computer for various values ofzeta. It is shown that, whenzetais sufficiently large, results similar to those for first order loops or single tuned circuits are obtained, i.e., the meansquare random jitter is almost proportional to the square root of the number of repeaters, and the mean-square systematic jitter is almost proportional to the number of repeaters. Whenzetais small the meansquare jitter increases exponentially as the number of repeaters is increased. This paper also describes the optimum value ofzeta, considering both the jitter accumulation and the transient response of the PLL, by using the number of repeatersNas a parameter. As a result, it is postulated that the optimum value ofzetais 5 to 8 whenNis 100, and 15 to 18 whenNis 1,000.     

一种单次精密时序电脉冲的产生方法

单次精密时序电脉冲系统是大型固体激光装置的神经中枢,大型固体激光装置需要数百路单次精密定时触发电脉冲来控制激光的运行和诊断。在一次发射周期,全装置需要的电脉冲时序持续2s以上,要求电脉冲相互间时间抖动小于100ps。因此提出了一种单次精密时序电脉冲的产生方法,按此方法研制出的多路时序触发系统已经成功应用在大型激光装置上。     

Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation

In this paper, we compare a shift register (SR) to a delay-locked loop (DLL) for flexible multiphase clock generation, and motivate why a SR is not only more flexible but often also better. For a given power budget, we show that a SR almost always generates less jitter than a DLL, assuming both are realized with current-mode logic. This is due to differences in jitter accumulation and the possibility to choose latch delays in a SR much smaller than the delays of DLL elements. For -phase clock generation, a SR also functions as a divide-by- and requires a voltage-controlled oscillator with times higher frequency. However, this does not necessary lead to more power consumption and can even have advantages like higher Q and less area for the inductors.     

Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division

This paper presents a new method for measuring random timing jitter or sinusoidal timing jitter in signals of telecommunication devices. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter. This new frequency division method is validated with experimental data from a serializer-deserializer device and a modulated signal source generating a 2.5 GHz FM signal.     

卫星数字调制解调器中的时钟抖动

介绍了时钟抖动的一些基本概念。针对卫星数字调制解调器中的时钟抖动问题进行了深入探讨,对于调制解调器中时钟抖动的产生机理、解决办法都做了深入分析。结合调制解调器中出现的两个时钟抖动问题,详细分析、讲解了时钟抖动在卫星数字调制解调器中的影响及问题的解决及应对措施。针对卫星数字调制解调器的开发和生产给出了两种行之有效的时钟抖动测试方法。     

数据传输系统中的定时抖动

本文介绍了通过数字锁相环减弱定时抖动的分析计算方法。导出了不经过积螺，经过不同方法积螺进行相位调整时的抖动改善量计算公式，并给出抖动改善量与有关参数的关系曲线，可作为数据传输系统设计定量环路的参考。     

Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits

The implementation of complex, high-performance digital functionality in nanometer CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This paper proposes the application of unified semi-empirical propagation delay variation models to estimate the effect of Process, power supply Voltage, and Temperature (PVT) variations on the timing response of nanometer digital circuits. Experimental results based on electrical simulations of circuits designed in 65, 45, and 32?nm CMOS technologies are presented demonstrating that the models can be used for the analytical derivation of delay variability windows and delay variability statistical distributions associated to process variations. This information can be used during the design and test processes. On one hand, it allows the robustness of a given circuit in the presence of PVT variations to be assessed in the design environment. On the other hand, it allows boundaries between expected functional windows and those associated to abnormal behaviors due to delay faults to be defined. The main advantage of the proposed approach is that the effect of process variations on circuits’ performance can simultaneously be analyzed with those of power supply voltage and temperature variations. Experimental results have also been obtained on several FPGA boards including nanometer-scale Xilinx? and Altera? devices. These results provide a proof-of-concept, on real circuits, of the practical usefulness of the models.     

Jitter Characteristic in Charge Recovery Resonant Clock Distribution

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.     

用于高速ADC的低抖动时钟稳定电路

介绍了一种用于高速ADC的低抖动时钟稳定电路.这个电路由延迟锁相环(DLL)来实现.这个DLL有两个功能:一是通过把一个时钟沿固定精确延迟半个周期,再与另一个沿组成一个新的时钟来调节时钟占空比到50%左右;二是调节时钟抖动.该电路采用0.35 μm CMOS工艺,在Cadence Spectre环境下进行仿真验证,对一个8 bit、250 Msps采样率的ADC,常温下得到的时钟抖动小于0.25 ps rms(典型的均方根).     

Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme

A new technique is presented for evaluating the performance of a popular type of timing recovery circuit for baseband synchronous pulse amplitude modulation (PAM) data signals. The timing circuit consists of a square-law device followed by a narrowband filter tuned to the pulse repetition frequency along with provision for reshaping the pulses entering the timing path (prefiltering). The output of the timing circuit is a nearly sinusoidal timing wave whose zero crossings indicate the appropriate sampling instants for demodulation of the PAM signal. For a random data sequence, the timing wave exhibits phase fluctuations which are strongly dependent on the pulse shapes entering the timing path and the passband shape of the narrow-band filter. Expressions for rms phase fluctuation in the timing wave as a function of the prefiltering and postfiltering characteristics of the filters preceding and following the square-law device are presented. These expressions have a form which is especially suitable for studying the case where the baseband PAM signal is band-limited to frequencies less than the pulse repetition frequency. A condition on prefiltering and postfiltering which gives error-free timing recovery is presented. Results obtained from some specific examples serve to illustrate several aspects of the timing recovery problem.     

一种新型低抖动快速锁定时钟稳定电路

介绍了一种新型低抖动快速锁定时钟稳定电路.该电路通过检测输入时钟信号的上升沿,产生一个尖峰脉冲和一个精确延迟半个周期的尖峰脉冲,共同组成一个稳定的低抖动时钟.该电路采用0.35 μm标准CMOS工艺库,在Cadence环境下进行仿真,在100 MHz输入时钟频率下,输出时钟抖动为56 fs,电路的功耗仅有35 mW.     

色散控制WDM孤子通信系统中的定时抖动

采用拉格朗日变分法在同时考虑本信道放大自发辐射 (ASE)噪声、相邻信道信号对本信道信号和ASE噪声等多种因素影响的情况下 ,分析了色散控制孤子的传输演化特性 ,给出了准稳态色散控制孤子传输动力学方程和定时抖动解析表达 ,并给出了三种扰动因素影响程度的比较。     

开关电流电路中的时钟馈入效应

本文采用ＭＯＳ开关的集总时变ＲＣ模型，对开关电流（ＳＩ）电路中的时钟馈入效应进行了详细的理论分析，导出了开关电流镜中钟馈电压和钟馈电流的表达式，从而揭示出了钟馈电压／电流与工艺参数、ＭＯＳ器件尺寸、时钟信号幅值及其下降沿斜率等之间的内在关系。用它可对ＳＩ电路中时钟馈入的影响进行快速预测。文中的理论分析与ＳＰＩＣＥ仿真结果相一致。所提供的结果对于设计高精度低功耗ＳＩ电路有应用价值。     

Asynchronous and Timing Jitter Insensitive Data Echo Cancellation

An approach to the implementation of asynchronous and timing jitter insensitive data echo cancellation is described. This approach introduces a small amount of jitter in the transmitted data signal, or alternatively in the received signal sampling, and uses a simple digital phase-locked loop together with the storage of two sets of echo canceler coefficients. The effect of derived timing jitter on the echo cancellation accuracy is completely eliminated for a loop timed transceiver (as in a digital subscriber loop network termination transceiver), and is easily reduced to negligible levels for a nonloop timed transceiver (as in a digital subscriber loop line card transceiver or a voiceband data modem). In the case of a voiceband data modem, this approach is one method to achieve asynchronous echo cancellation without the need to recover and resample a continuous-time far-end data signal.     

时钟抖动和相位噪声对数据采集的影响

随着采样频率和A/D变换器位数的增加,时钟抖动和相位噪声对数据采集系统性能的影响更加显著.从相位噪声的双边带功率谱密度出发,详细分析了相位噪声和周期间抖动之间的联系,指出了相位噪声的不同频段对周期间抖动的影响,讨论了数据采集信噪比与时钟抖动和相位噪声之间的关系;并通过仿真给予定量的计算,对时钟源和数据采集系统的设计提供了一些建议;最后,利用某雷达数据采集系统进行实验,给出了相关实验结果.     

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits

In this paper, we analyze the occurrence of jitter due to random and deterministic disturbances in nonautonomous current-mode logic circuits. First, we present an analytical model that explains the transformation of noise into jitter as a linear time-variant process, with its time-domain impulse response function and a frequency-domain system function. The model is then used to analyze jitter in two different circuits, with different sources of noise. In the first example, we use the model to predict jitter due to device noise in a frequency divider, and identify devices that are the main contributors to the jitter. In the second example, we examine jitter of a buffer with deterministic ground noise. Jitter predictions are compared to the results obtained through exhaustive simulation. According to the comparison, the method predicts jitter with an error of up to 3.4%.      

Timing Jitter Transfer Function in the Temporal Talbot Effect

We report the predicted timing jitter transfer function for the temporal Talbot effect. The results, consistent with previous theoretical analyses, indicate a clear low-pass-like behavior, with significant jitter attenuation below a specific jitter cutoff frequency, and visible resonant peaks for frequencies satisfying secondary Talbot conditions. The observed transfer function makes the Talbot effect especially interesting for jitter mitigation in all-optical clock schemes.     

特殊分频电路设计

在数字系统中各个模块所需的时钟频率往往不相同,通常采用分频的方法由系统时钟得到所需频率。计数器作为一种典型分频电路有容易实现、波形均匀等优点,其遵循二分频原理也就要求在应用中系统时钟必须是输出频率整数倍为前提。详细介绍了2种特殊的分频电路积分分频电路和半整数分频电路,这2种电路分别基于分数分频和小数分频的原理,突破了计数器电路的局限性,具有较高的应用价值。