AM and FM Noise of BARITT Oscillators

AM, FM, and baseband noise of a BARITT diode oscillator in the range 100 Hz-50 kHz off the carrier has been measured under various operating conditions. A simple calculation has been made, relating the baseband noise to the oscillator AM and FM noise via measured amplitude and frequency modulation sensitivities and the results have been compared with the noise measured. It is shown that, depending on the bias current applied, both AM and FM noise performance can be degraded by up-conversion. Complete removal of up-converted noise requires a high-impedance low-noise bias supply since both the diode noise and bias supply noise at baseband frequencies may be significant when up-converted. Even with all modulation suppressed, the AM and FM noise has a flicker component almost completely correlated with the diode flicker noise at baseband frequencies. The RF power dependence of the AM and FM noise has also been investigated. It is shown that the BARITT oscillator noise compares very favorably with that of IMPATT's and TEO's. Values of -142 dB/100 Hz (AM noise) and 3.5 Hz/(100 Hz)/sup 1/2/ for Q/sub ext/ = 200 (FM noise) have been measured at 30 kHz off the carrier.     

Ultrabroadband GaAs monolithic amplifier

A 500 kHz?2.8 GHz, 13.5 dB GaAs monolithic amplifier has been developed for gigabit baseband pulse amplification. Input VSWR was reduced using inter-gate-drain negative feedback. The interstage circuit is a DC coupled circuit consisting of a high impedance transmission line.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

Frequency division multiplexed microwave and baseband digitaloptical fiber link for phased array antennas

A frequency-division multiplexed optical fiber link is described in which microwave (1-8 GHz) and baseband digital (1-10 Mb/s) signals are combined electrically and transmitted through a direct-modulation microwave optical link. The microwave signal does not affect bit error rate (BER) performance of the Manchester-coded baseband digital data link. The baseband digital signal affects microwave signal quality by generating second-order intermodulation noise. The intermodulation noise power density is found to be proportional to both the microwave input power and the digital input power, enabling the system to be modeled as a mixer (AM modulator). The conversion loss for the digital signal is approximately 68 dB for a 1-GHz microwave signal and is highly dependent on the microwave frequency, reaching a minimum value of 41 dB at 4.5 GHz corresponding to the laser diode relaxation oscillation frequency. It is shown that Manchester coding on the digital link places the intermodulation noise peak away from microwave signal, preventing degradation of close-carrier phase noise (<1 kHz offset). A direct trade-off between intermodulation noise and digital link margin is developed to project system performance     

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described.Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications.The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing.The calibra...     

A Compatible CMOS-JFET Pulse Density Modulator for Interpolative High-Resolution A/D Conversion

The analog part of a high-resolution A/D converter has been integrated in a compatible CMOS-JFET technology. The circuit, which forms a pulse-density modulator (PDM), can be operated at sample rates up to 12 MHz and reaches a peak SNR of 84 dB over a baseband of 20 kHz. This corresponds to approximately 14-bit A/D resolution.     

A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter

A low-spurious low-power 12-bit 160-MS/s digital to analog converter (DAC) for baseband wireless transmitter is proposed and demonstrated. Degenerated current switches are introduced and benefits of using them are discussed. Mismatch behavior under packaging-induced die stress is also presented. The mobility shift caused by package stress inherited from a thin-die is a dominant source of I/Q mismatch. A 2-channel I/Q DAC core consumes 4 mA with a 1.3/2.6 V dual supply. The 0.13 mm² I/Q DAC core fabricated in 90-nm digital CMOS process with a highly-integrated digital processor achieves 74 dB SFDR, 55 dB SNDR, and -73 dB THD for a 975 kHz sinusoid at 153.6 MS/s sample rate     

Division-free duplex for wireless applications

Division-free duplex is proposed for future wireless systems, thus providing simultaneous duplex radio transmission on a division-free basis. The required duplex isolation can be achieved by electronic interference cancellation operating at both RF and baseband, with results from an experimental RF system yielding some 72 dB duplex isolation at 1.8 GHz for 200 kHz channelisation     

Design of a high-order single-loop ∑△ ADC followed by a decimator in 0.18 μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital con verter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm~2.     

A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

A 400-Ms/s frequency translating bandpass sigma-delta modulator

A bandpass Σ-Δ modulator is described in this paper that uses frequency translation inside the Σ-Δ modulator loop to take advantage of the attributes of both continuous-time and discrete-time circuits. A CMOS direct-conversion modulator digitizes a 200 kHz intermediate-frequency signal centered at 100 MHz and produces baseband I/Q outputs with a peak signal-to-noise ratio of 54 dB. Images due to I/Q mismatches are suppressed by 50 dB. This 0.35-μm digital CMOS chip operates from a 2.7/3.3-V supply, dissipates 330 mW, and occupies 3.2 mm²     

A broad-band VHF mixer exhibiting high image rejection over a multidecade baseband frequency range

Image-suppressing frequency converters operating over greater than octave RF and LO input bandwidths in the VHF frequency range are described. The devices, designed for RF to video conversion, exhibit very flat conversion loss response and greater than 34 dB rejection of the undesired sideband at any baseband frequency between 186 kHz and 50 MHz.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

A new low-cost demodulator for 2.4 GHz ZigBee receivers

A new low-cost demodulator for ZigBee receivers satisfying requirements of IEEE802.15.4 standard is presented, which is designed for ISM 2.4 GHz band and based on Zero-IF receivers. This demodulator extracts symbols directly from baseband signal rather than recovering PN code chips, so its structure is simple. Two main techniques are used to improve the performance of demodulator. One is Phase-Axis Crossing Detector (PACD) which detects the phase correlation of baseband signal. The other is symbol synchronization and sampling clock correction algorithm. The result shows that this demodulator performance, Symbol Error Rate (SER) and Packet Error Rate (PER) meet IEEE 802.15.4TM standard requirements and the demodulator can handle frequency offset in excess of 200 kHz, involving a Zero-IF receiver with a Noise Figure (NF) lower than 17 dB, which is easily implemented in standard CMOS technology.     

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.     

一种用于900MHz射频识别(RFID)读写器芯片的1.8VCMOS直接变频接收机

设计了针对解决900MHz RFID读写器收发机芯片中本地载波干扰问题而优化的直接变频接收机,并在0.18μm 1P6M混合信号CMOS工艺上实现验证.设计中使用了一种串联反馈结构的基带放大器以达到同时实现无源混频器输出缓冲,直流消除以及信号放大的功能.实际测量显示,该接收机的输入1dB压缩点为-4dBm,当中频信号解调信噪比要求为10dB时,可达到的灵敏度为-70dBm.该接收机与整个收发机集成在同一块芯片中,使用1.8V电源电压,工作时静态电流为90mA.     

A UHF mobile telephone system using digital modulation: Preliminary study

A UHF mobile telephone system using digital modulation is described. The system uses on-off keying of an 836-MHz carrier, the code being supplied by an adaptive delta coder with a clock frequency of 50 kHz. The maximum audio baseband signal-to-noise ratio is approximately 30 dB. The mobile receiver employs space diversity in a maximal-ratio combiner. Due to the use of amplitude modulation of the carrier rather than exponential modulation, the diversity receiver is very simple. The system was tested in the laboratory and in the field. Field tests were made in suburban and urban areas. For the four-branch system, threshold occurred at an average IF signal-to-noise ratio of approximately 12 dB.     

A frequency agile monolithic QPSK modulator with spectral filteringand 75 Ω differential line driver

This monolithic modulator combines both digital signal processing and analog techniques to realize a high bit-rate quadrature phase-shift keyed (QPSK) modulator. It includes a digital baseband pulse shaping network, analog quadrature modulator, agile carrier generator, spectral shaping, and transmit power control for interfacing to wireline transmission media. Nominal data rates are 256 kbit/s with a carrier range of 8.096-20.128 MHz in 32 kHz steps. Maximum output level is 62 dBmV into a 75 Ω load. The features of 1.2 μm mixed signal BiCMOS technology permit both signal processing and power line drivers to be collocated while achieving better than 85 dB cross-talk isolation     

A 250-kHz 94-dB double-sampling /spl Sigma//spl Delta/ modulation A/D converter with a modified noise transfer function

This paper presents a high-order double-sampling single-loop /spl Sigma//spl Delta/ modulation analog-to-digital (A/D) converter. The important problem of noise folding in double-sampling circuits is solved here at the architectural level by placing one of the zeros in the modulator's noise transfer function at half the sampling frequency instead of in the baseband. The resulting modulator is of fifth order but has the baseband performance of a fourth-order modulator. Through the use of an efficient switched-capacitor implementation, the overall circuit uses only four operational amplifiers and hence, its complexity is similar to that of a fourth-order modulator. An experimental 1-bit modulator was designed for an oversampling ratio of 96 and a bandwidth of 250 kHz at a 3.3-V supply in a conservative 0.8-/spl mu/m standard CMOS process. Due to the double-sampling, the sampling frequency is 48 MHz, although the circuits operate at a clock frequency of only 24 MHz. The circuit achieves a dynamic range of 94 dB. The peak signal-to-noise ratio and signal-to-noise-plus-distortion ratio were measured to be 90 and 86 dB, respectively. The power consumption of the complete circuit including clock drivers and output pad drivers was 43 mW. The analog blocks (opamps, comparators, etc.) consume 30 mW of this total.