共查询到20条相似文献,搜索用时 31 毫秒
1.
G. Molas M. Bocquet H. Grampeix J.P. Colonna P. Brianceau C. Bongiorno G. Pananakakis B. De Salvo 《Microelectronic Engineering》2008,85(12):2393-2399
In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO2/HfAlO/SiO2 triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250 °C. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler-Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results. 相似文献
2.
E. Amat R. Rodríguez M. Nafría X. Aymerich J.H. Stathis 《Microelectronics Reliability》2007,47(4-5):544
The substitution of the SiO2 gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO2 thickness. To improve the quality of the high-k/Si interface a very thin SiO2 film is grown between both materials. In this work, HfO2/SiO2 stacks with different SiO2 thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO2 in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO2 interfacial layer influences the advanced stages of the stack degradation. 相似文献
3.
In this work a high-k insulating film is deposited on the SiO2 tunnel oxide of MOS capacitors designed for non-volatile memory applications. The advantages of this approach derive from the asymmetric band diagram, which lowers the Fowler–Nordheim tunnel erase barrier, without affecting the program operation. This results in lower erase voltage and much shorter erase times. In fact, in the proposed structure the erase voltage is about 20% lower and the erase current three thousands times greater than in conventional MOS with pure-SiO2 tunnel oxide and the same equivalent oxide thickness (15 nm). At the same time, the larger physical thickness prevents from charge loss, and guarantees data retention. The goal of such device is to improve the memory performances without degrading reliability. 相似文献
4.
During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO2 films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO2 as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO2/TiO2 MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness. 相似文献
5.
G. Ghidini N. GalbiatiC. Scozzari A. SebastianiR. Piagge A. Del VittoP. Comite M. AlessandriP. Tessariol I. BaldiE. Moltrasio E. Mascellino 《Microelectronic Engineering》2011,88(7):1182-1185
The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits.Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO2-Si3N4-SiO2 stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and de-trapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application. 相似文献
6.
Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO2 and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO2/HfSiON with a U-shape nitrogen profile and a like-Si/SiO2 interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO2 and 1.2-nm HfSiON exhibits the lowest gate leakage. 相似文献
7.
P. Chakraborty S.S. Mahato M.K. Bera S.K. Samanta C.K. Maiti 《Microelectronic Engineering》2009,86(3):299-302
Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si3N4) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO2 as a blocking oxide in p-Si/SiO2/AlN/SiO2/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented. 相似文献
8.
Youhei Sugimoto Hideto Adachi Keisuke Yamamoto Dong Wang Hideharu Nakashima Hiroshi Nakashima 《Materials Science in Semiconductor Processing》2006,9(6):1031
High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO2/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfOx and SiO2. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfOx/SiO2/Si to HfSixOy/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO2. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO2. 相似文献
9.
ZrO2 with a κ value of 30 grown by atomic layer deposition has been integrated as charge trapping layer alternative to Si3N4 in TANOS-like memory capacitors, with Al2O3 as blocking oxide, SiO2 as tunnel oxide and TaN metal gate. The fabricated device featuring 24 nm ZrO2 exhibits efficient program and erase operations under Fowler-Nordheim tunneling when compared to a Si3N4 based reference device with similar EOT and fabricated under the same process conditions. The effect of stack thermal budget (900-1030 °C range) on memory performance and reliability is investigated and correlated with physical analyses. Finally, scaling ZrO2 down to 14 nm allows program and erase at lower voltages, even if the trapping efficiency and retention of these device need further improvements for the integration of ZrO2 in next generation charge trapping nonvolatile memories. 相似文献
10.
Jungwoo Oh Prashant Majhi Raymond Joe Yasushi Akasaka Tsunetoshi Arikado 《Microelectronic Engineering》2008,85(8):1804-1806
The authors report on fully strained Si0.75Ge0.25 metal-oxide-semiconductor capacitors with HfSiO2 high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si0.75Ge0.25 films are directly grown on Si substrates below the critical thickness. HfSiO2 high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO2 gate oxides by >100×. Interfacial oxide of the HfSiO2/Si0.75Ge0.25 stack consists primarily of SiO2 with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO2/SiGe gate stack. 相似文献
11.
Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling
Martin M. Frank Chiara MarchioriJohn Bruley Jean FompeyrineVijay Narayanan 《Microelectronic Engineering》2011,88(7):1312-1316
We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO2 formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO2-SiO2 intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors. 相似文献
12.
Zeynep Çelik-Butler Siva Prasad Devireddy Philip Tobin 《Microelectronics Reliability》2009,49(2):103-112
A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high-k), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high-k/interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high-k/interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C-V measurements were performed in the 78-350 K temperature range on TaSiN/HfO2 n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO2 by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO2 resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high-k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1-100 Hz frequency range at temperatures of 78-350 K for both gate stacks. 相似文献
13.
Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si83Ge17 by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×1010 cm−2 eV−1 was obtained. 相似文献
14.
We demonstrate low-trap-density HfON film made by the molecular-atomic deposition (MAD) technique, which is an Ar/N2 plasma jet assisted physical vapor deposition process. This high-k HfON can be deposited on top of the nearly trap-free MAD-Si3N4 to form a single-side crested tunnel barrier. The Al/(HfON-Si3N4)/Si capacitor structure with HfON/Si3N4 stack as the tunnel barrier demonstrates steeper I-V slope than that of a single layer SiO2 with the same EOT, and is readily applicable to improve the programming speed and data retention of flash memories. 相似文献
15.
F. Ferdousi J. Sarkar S. Tang D. Shahrjerdi T. Akyol E. Tutuc S.K. Banerjee 《Journal of Electronic Materials》2009,38(3):438-442
This work presents vertical flash memory devices with protein-assembled PbSe nanocrystals as a floating gate and Al2O3 as a control oxide. The advantage of a vertical structure is that it improves cell density. Protein assembly improves uniformity
of nanocrystals, which reduces threshold voltage variation among devices. The introduction of Al2O3 as a control oxide provided lower voltage/faster operation and hence less power consumption compared with the devices fabricated
with SiO2. The integration of Al2O3 appeared to be compatible with the protein assembly approach. In conclusion, Al2O3 has the potential to become the high-k control oxide due to its relatively high electron/hole barrier heights, and high permittivity. 相似文献
16.
《Microelectronics Journal》2007,38(6-7):783-786
For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO2-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node. 相似文献
17.
High permittivity materials have been required to replace traditional SiO2 as the gate dielectric to extend Moore’s law.However,growth of a thin SiO2-like interfacial layer(IL) is almost unavoidable during the deposition or subsequent high temperature annealing.This limits the scaling benefits of incorporating high-k dielectrics into transistors.In this work,a promising approach,in which an O-scavenging metal layer and a barrier layer preventing scavenged metal diffusing into the high-k gate dielectric are used to engineer the thickness of the IL,is reported. Using a Ti scavenging layer and TiN barrier layer on a HfO2 dielectric,the effective removal of the IL and almost no Ti diffusing into the HfO2 have been confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy. 相似文献
18.
Martin M. Frank SangBum Kim Stephen L. Brown John Bruley Matthew Copel Marco Hopstaken Michael Chudzik Vijay Narayanan 《Microelectronic Engineering》2009,86(7-9):1603-1608
We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high-k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO2 can be scaled to capacitance equivalent thickness in inversion (Tinv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si3N4 and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher-k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO2 as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO2 at the poly-Si contact. We further address the performance of Si3N4 and HfO2 as oxygen barrier layers. 相似文献
19.
20.
G. Molas M. Bocquet E. Vianello L. Perniola H. Grampeix J.P. Colonna L. Masarotto F. Martin P. Brianceau M. Gély C. Bongiorno S. Lombardo G. Pananakakis G. Ghibaudo B. De Salvo 《Microelectronic Engineering》2009,86(7-9):1796-1803
In this paper, we evaluate the potentiality of high-k materials (Al2O3, HfO2 and HfAlO) for interpoly application in non-volatile memories. A study of the leakage currents of high-k based capacitors allowed to discuss the retention performances at room and high temperatures of high-k interpoly dielectrics. High-k materials are then integrated as control dielectrics in silicon nanocrystal and SONOS (Si/SiO2/Si3N4/SiO2/Si) memories. The role of the high-k layer on the memory performances is discussed; a particular attention being devoted to the retention characteristics. Analytical models, combined with experimental results obtained on various structures allowed to analyze the mechanisms involved during retention. 相似文献