一种低电源电压高精度带隙基准源的设计

如果要设计一个低电源电压的带隙基准源,就会遇到电源电压和带隙基准参考的性能之间的矛盾,这是因为带隙基准本身的失调和1/f噪声(又称闪烁噪声)所致。通过斩波技术的应用,带隙基准的输出精度得到大幅度的提升,同时1/f噪声也得到了有效的抑制。     

一种低噪声、高电源抑制的低压降稳压器

实现了一种低噪声、高电源抑制(PSR)的低压降线性稳压器。设计了一个新型的低温度系数高电源抑制的带隙基准源,这个基准源可以为稳压电路提供参考电压。采用带有低通滤波器的预调制电路来降低稳压器的输出噪声和高频电源行波干扰。测试结果表明,该稳压器的线性调整率为0.57mV/V,负载调整率为0.1mV/mA,100kHz下的交流电源抑制为-60dB。在10Hz～1MHz频率范围内,仿真得到的总输出噪声只有4μVrmss。该稳压器采用上华CSMC0.6μm、5V混合信号CMOS工艺设计,有效芯片面积为600μm×560μm。     

国产线性稳压器电离总剂量效应及损伤研究

选择国产三端可调正输出稳压器进行60Co-γ电离辐照实验,研究其电离总剂量效应及损伤变化规律.实验结果发现,基准电压、电压调整率、电流调整率、纹波抑制比是敏感参数,在电离辐射环境中发生明显的退化.结合电路结构,分析了敏感参数退化的原因,探讨了基准电压源和误差放大器等内部关键模块对稳压器抗辐照性能的影响.     

典型双极能隙基准源的瞬时电离辐射效应分析

分析了典型双极型二管和三管能隙基准源受瞬时电离辐射后的输出响应,以及以双极能隙基准源为基本电路的集成稳压器的瞬时辐射效应,并对含典型三管能隙基准源的集成稳压器L7805芯片进行了瞬时电离辐射实验验证。实验结果表明,基准源受辐射后输出电平降至零电平附近,致使稳压器输出降低,并且电平恢复时间与剂量率成对数关系,与理论分析结果一致。     

一种低噪声高电源抑制比CMOS低压差线性稳压器

提出了一款基于标准0.18μm CMOS工艺的低噪声高电源抑制比(PSRR)CMOS低压差线性稳压器(LDO),其中包括了带隙基准电路。对LDO和带隙基准电路的噪声和电源抑制进行了建模分析,并得出了电路设计原则。根据设计原则使用两级误差放大器实现了低噪声高电源抑制性能,并且通过合理的频率补偿保证了电路稳定。测试结果显示,LDO输出在-40¹20℃温度范围内的温度系数约为48×10-6/℃;在1120℃温度范围内的温度系数约为48×10-6/℃;在1¹00kHz频率范围内输出噪声电压约为37.3μV;在1kHz和1MHz处的PSRR分别大于60dB和35dB;芯片总面积约为0.27mm2,无负载电流约为169μA。     

一种低电源电压带隙基准的设计

设计了一种可以工作在1V电源电压下的CMOS带隙基准。普通的带隙基准是通过VBE(双极型晶体管的基极-发射极电压)和kVT(VT=k·T/q)的和来实现输出基准电平,由于器件本身的特性而决定了其输出电平一般在1.25V左右。本文的带隙基准通过两个分别正比于VBE和kVT和的电流的叠加来实现低电平输出。使用SMIC0.35um模型仿真,得该电路的输出电平为506mV。     

一种低温度系数高驱动能力的带隙基准电路

基于Grace 0.18μm标准CMOS工艺,设计了一种带低压差线性稳压器的低温度系数带隙基准源.仿真结果表明,在1.8V供电下,带隙基准电路从电源电压上抽取约340 μA电流,在-40℃～85℃温度范围内,输出电压为900.24 mV±0.222 mV,温度系数达到5×10-6/℃,在1kHz频率下,电源抑制比约为5...     

宽负载范围的高PSRR线性电源研究

研究分析了线性稳压电源中电源对稳压输出的噪声影响途径,提出了一种与负载无关的高PSRR线性稳压器电路,为减小电源噪声对LDO模块电路的影响,基于带隙基准源内部的自建电压实现高压和低噪声隔离,抑制了传统结构带来的功耗、 面积和噪声问题,基于0.18μｍ、４０ Ｖ 高压BCD工艺进行了具体电路设计与芯片实现,经过全面验证,在电源电压为 4.5Ｖ 到32 Ｖ,输出电容为2.2μＦ,最大负载电流为200ｍＡ 的条件下LDO可提供3.3Ｖ的稳定电压源,空载时PSRR可达到80.5,ｄＢ负载为200ｍＡ下PSRR仍然高达80.23ｄＢ,变化率仅为0.001ｄＢ/ ｍＡ,实现了与负载无关的高PSRR 线性稳压器设计。     

用1/f噪声表征VDMOS器件的抗辐照性能

介绍了用于航空航天DC/DC转换器中的VDMOS器件和电离辐照前后低频1/f噪声的变化.研究了电离辐照情况下VDMOS器件的阈值电压漂移、跨导的退化对1/f噪声幅值、γ值的影响.结合实验,比较器件1/f噪声幅值和γ值在辐照前后的变化,对其抗辐照性能做表征研究.对VDMOS器件在辐照前后的变化做了分析,从γ值分形的角度简要说明辐照对器件产生的影响.     

LED显示屏的恒流驱动电路的设计

介绍了一种LED显示屏的恒流驱动电路,该电路包括输出控制部分电源电压的低压差线性稳压器、产生多路基准电压的带隙基准电压源、误差放大器、缓冲器、多个大功率MOS管以及取样MOS管五个部分,并且重点介绍了其中的低压差线性稳压器和带隙基准电压源的具体实现电路,能够更好的减少振荡,提高精度。通过上述恒流驱动电路为多路LED提供恒定的0.4V的驱动电流。     

1/f noise as a reliability indicator for subsurface Zener diodes

It is shown from accelerated life tests and noise measurements that the degradation in reference voltage for subsurface Zener diodes is strongly correlated with 1/f noise in the devices. The larger the initial 1/f noise of a diode is, the earlier its degradation occurs. Compared with dc parameters, 1/f noise is more sensitive to the slight change in the structure of the devices subjected to operation or test stresses. In the mechanism analysis, the degradation and the 1/f noise are attributed to similar physical origin, and both are related to dislocations in the space-charge region of p–n junction. Based on the results, a 1/f noise screening approach is proposed for the high reliability application of the devices.     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

一种氮化镓高迁移率晶体管的栅电流噪声模型

This work presents a theoretical and experimental study on the gate current 1/f noise in Al Ga N/Ga N HEMTs. Based on the carrier number fluctuation in the two-dimensional electron gas channel of Al Ga N/Ga N HEMTs, a gate current 1/f noise model containing a trap-assisted tunneling current and a space charge limited current is built. The simulation results are in good agreement with the experiment. Experiments show that, if Vg Vx, gate current 1/f noise comes from not only the trap-assisted tunneling RTS, but also the space charge limited current RTS. This indicates that the gate current 1/f noise of the Ga N-based HEMTs device is sensitive to the interaction of defects and the piezoelectric relaxation. It provides a useful characterization tool for deeper information about the defects and their evolution in Al Ga N/Ga N HEMTs.     

Change in d.c. and 1/f noise characteristics of n-submicron MOSFETs due to hot-carrier degradation

Hot-carrier stress and its influence on d.c. and 1/f noise characteristics in submicron n-channel MOSFETs was investigated. From a 0.5 μm CMOS technology we observed a negative shift in the threshold voltage and a decrease in the drain current. The degradation increases the series resistance on the drain side. In most cases, the relative 1/f noise in the drain current also increases. A degraded device is often found to be noisier in its reverse mode than in its normal mode. The novel material is that the normalized 1/f noise analysis in terms of the 1/f noise parameter α is a more sensitive diagnostic tool for hot-carrier degradation in submicron MOSFETs than S_I (

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) and some results are qualitatively explained in terms of mobility fluctuations.     

Modeling of current transport and 1/f noise in heterojunction bipolar transistors

An analytic model is proposed to determine the effect of band offsets at heteroemitter interface on the current transport and 1/f noise in heterojunction bipolar transistors (HBTs). The proposed model uses the modified form of drift-diffusion formalism, which requires that the net recombination rates be proportional to the densities of other type carriers across the heterointerface. The numerical analysis of the current–voltage and 1/f noise characteristics of Npn AlGaAs/GaAs HBT and npn GaAs BJT demonstrates that the role of band offsets at heteroemitter interface in the overall current transport and 1/f noise is very important in HBTs at low forward biases. The junction resistance due to diffusing minority electrons is much stronger (weaker) at small (high) forward biases than that due to recombined electrons and holes across the heteroemitted space charge region in both Npn AlGaAs/GaAs HBTs and npn GaAs BJTs.     

A wavelet analysis of 1/f and white noise in microwave transistors

The results of a computer-controlled experiment devoted to on-line measurements of the wavelet transform (WT) of low-frequency electronic noise voltage in bipolar microwave transistors are presented. We measure the average recurrence time of fluctuations of the WT coefficients occurring selectively in limited time and at frequency intervals. We detect two quite different behaviors in such recurrence times in the 1/f and white noise regimes.     

Degradation of InGaAs/InP single heterojunction bipolar transistors under high energy electron irradiation

The d.c. characteristics of InGaAs/InP single heterojunction bipolar transistors (SHBTs) were studied for the first time under high energy (1 MeV) electron radiation of cumulative dose up to 5.4×10¹⁵ electrons/cm². No degradation was observed for electron doses below 10¹⁵/cm². For electron doses greater than 10¹⁵/cm² the following degradation effects were observed: (1) decrease in collector current; (2) decrease in current gain up to 50%; (3) an increase in collector saturation voltage by 0.2–0.8 V depending on base current; and (4) increase in output conductance. The degradation of collector current and current gain are thought to be due to increased recombination caused by radiation-induced defects in the base–emitter junction. The increase in collector saturation voltage is attributed to an increase in emitter contact resistance after irradiation. The increase in the avalanche multiplication in the reverse biased base–collector junction caused by radiation induced defects is believed to be responsible for increased output conductance after irradiation.     

一种低温漂的CMOS带隙基准电压源的研究

为了满足深亚微米级集成电路对低温漂、低功耗电源电压的需求,提出了一种在0.25μm N阱CMOS工艺下,采用一阶温度补偿技术设计的CMOS带隙基准电压源电路。电路核心部分由双极晶体管构成,实现了VBE和VT的线性叠加,获得近似零温度系数的输出电压。T-SPICE软件仿真表明,在3.3 V电源电压下,当温度在-20~70℃之间变化时,该电路输出电压的温度系数为10×10-6/℃,输出电压的标准偏差为1 mV,室温时电路的功耗为5.283 1 mW,属于低温漂、低功耗的基准电压源。     

Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface

The impact of halo implantation angle on the low-frequency noise of short channel n-MOSFET is reported. The low-frequency noise is degraded with larger tilt angle for the same implant dose and energy. The higher dose/energy of the halo implant with larger tilt angle further enhances the degradation of low-frequency noise. The larger halo angle introduces non-uniform doping distribution and creates the non-uniform threshold voltage along the channel. Additional traps can be created near the oxide/semiconductor interface due to boron pileup due to larger tilt angle. A quantitative analysis supported by experimental results confirm that the degradation of 1/f noise is due to the combined effect of non-uniformity in threshold voltage along the channel and the creation of extra trap charges near the oxide-semiconductor interface (near-interfacial charges).     

低压CMOS带隙电压源

介绍了CMOS带隙电压源的基本原理,并根据目前CMOS集成电路工艺发展对低电源电压的要求,详细地分析了几种能产生低输出电压且能兼容标准CMOS工艺的CMOS带隙电压源电路.这些电路所需的电源电压只有1V左右,并且都能够输出1V以下具有零温度系数的参考电压,其中有些电路的输出电压可以由电阻的比值来调节,因而可以增加电路设计的灵活性.本文还对低压CMOS带隙电压源电路的低频和高频噪声特性进行了深入分析,提出了改善输出参考电压噪声特性的途径.