Calibration-free 14b 70MS/s 0.13 /spl mu/m CMOS pipeline A/D converters based on highmatching 3D symmetric capacitors

A 14b 70MS/s pipeline A/D converter (ADC) in a 0.13 mum CMOS process employs signal insensitive 3D fully symmetric capacitors for high matching accuracy without any calibration scheme. The prototype ADC with a die area of 3.3 mm² shows measured differential and integral nonlinearities of 0.65LSB and 1.80LSB, respectively, at 14b     

一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

一种10bit双通道流水线SAR ADC设计

为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型（SAR）模数转换器（ADC）。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm2。ADC的微分非线性和积分非线性分别小于0.36 最低有效位（LSB）和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 MS/s。运行频率为230 MS/s和260 MS/s的ADC的功率消耗分别为13.9 mW和17.8 mW。     

A 360 fJ/conversion-step, 14-bit, 100 MS/s,digitally background calibrated pipelined ADC in 130-nm CMOS

This paper describes a 14-bit digitally background calibrated pipeline analog-to-digital converter (ADC) implemented in a mainstream 130-nm CMOS technology. The proposed calibration technique linearizes the digital output to correct for errors resulting from capacitor mismatch, finite amplifier gain, voltage reference errors and differential offsets. The software-based calibration technique requires quite modest digital resources and its estimated dynamic power is under 1 % of the ADC power consumption. After calibration, the 14-bit ADC achieves a measured peak Signal-to-Noise-plus-Distortion-Ratio of 71.1 dB at 100 MS/s sampling rate. The worst-case integral nonlinearity is improved from 32.9 down to 4 Least-Significant-Bits after calibration. The chip occupies an active area of 1.25 mm² and the core ADC (S/H+analog+digital power) consumes 105 mW. The Figure-of-Merit is 360 fJ per conversion-step.     

A low power and small area digital self-calibration technique for pipeline ADC

A digital self-calibration implementation with discontinuity-error and gain-error corrections for a pipeline analog-to-digital converter (ADC) is presented. In the proposed calibration method, the error owing to each reference unit capacitor of the multiplying D/A converter is measured separately using a calibration capacitor and an enhanced resolution back-end pipeline ADC acting as an error quantizer. The offset and finite open loop DC-gain of the operational amplifier and capacitor mismatches, the reference voltage mismatch can all be calibrated. The calibration can be achieved by that only used addition and subtraction. Hence, it needs low power and area consuming. A prototype ADC with the proposed calibration was fabricated on a 0.5 μm double-poly triple-metal CMOS process. The power consumption and area of the calibration circuit are only 10.1 mW and 1.05 mm², respectively. At a sampling rate of 30 MS/s, the calibration improves the DNL and INL from 2.59 LSB and 14.98 LSB to 0.72 LSB and 1.82 LSB, respectively. For a 1.25 MHz sinusoidal signal, the calibration improves the signal-to-noise-distortion ratio and spurious-free dynamic range from 43.1 dB and 52.1 dB to 75.51 dB and 83.61 dB, respectively. The 12.25 effective number of bits at 30 MS/s ADC consumes a total power of 136 mW.     

An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage

A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10⁴ clock cycles.     

采用改进型1.5位/级结构的10位100MHz流水线模数转换器

介绍了一个采用改进型1.5位/级结构的10位100MHz流水线结构模数转换器.测试结果表明,模数转换器的信噪失真比最高可以达到57dB,在100MHz输入时钟下,输入信号为57MHz的奈奎斯特频率时,信噪失真比仍然可以达到51dB.模数转换器的差分非线性和积分非线性分别为0.3LSB和1.0LSB.电路采用0.18μm混合信号CMOS工艺实现,芯片面积为0.76mm2.     

A 14-b 20-Msamples/s CMOS pipelined ADC

The capacitor error-averaging technique, updated with look-ahead decision and digital correction, is used to demonstrate a 14-b 20-Msamples/s pipelined analog-to digital converter (ADC) with no trimming or calibration. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The prototype in 0.5-μm CMOS occupies an area of 4.5×2.4 mm² and consumes 720 mW at 5 V     

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5/spl times/2.3 mm/sup 2/ in a 0.18-/spl mu/m dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80/spl deg/C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.     

A 14–10 b dual-mode low-noise pipeline ADC for high-end CMOS image sensors

This work proposes a low-noise four-stage pipeline ADC operating at 14 b 50 MS/s and 10 b 70 MS/s for high-end CIS applications. In the 10 b 70 MS/s mode, the last-stage MDAC and flash ADC are turned off rather than the first-stage MDAC and flash ADC for the same input-referred noise in both modes. The proposed ADC shares a single amplifier for the first- and second-stage MDACs to reduce power consumption and chip area. The amplifier thermal noise of the SHA and MDACs is minimized by adjusting the trans-conductance of input and current-source transistors while two separate reference voltage drivers for the MDACs and the flash ADCs reduce the switching noise. The prototype ADC in a 0.13 μm CMOS technology providing 0.35 μm thick-gate-oxide transistors shows the measured DNL and INL within 0.79 and 2.54 LSB in the 14 b mode, and 0.53 and 0.44 LSB in the 10 b mode, respectively. The ADC shows the maximum SNDR and SFDR of 68.5 and 86.7 dB in the 14 b 50 MS/s mode, and the SNDR and SFDR of 60.5 and 77.8 dB for the 10 b 70 MS/s mode, respectively. The ADC with the measured input-referred noise of 1.20 LSB_rms/14 b consumes 192.9 mW at the 14 b 50 MS/s, and 184.9 mW in the 10 b 70 MS/s mode with 3.3/1.2 V dual supplies.     

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.     

A Single Analog-to-Digital Converter That Converts Two Separate Channels (I and Q) in a Broadband Radio Receiver

An analog-to-digital converter (ADC) architecture that simultaneously converts two channels is presented. The ADC is intended for use in portable broadband radio receivers that employ in-phase (I) and quadrature (Q) signal paths and will provide an optimal combination of low cost, low power, and high performance. The architecture is pipeline based and employs two separate first stages followed by shared stages for the remainder of the pipeline. A clock generation system for generating all of the required nonoverlapping clock phases is also presented. A prototype ADC with 10 bit resolution and a 40 MHz sample rate that employs the proposed ADC architecture has been fabricated using a 90 nm all-digital CMOS process and occupies an area of 1.727 mm² for a per-channel area of 0.864 mm². The measured performance for the two-channel ADC is a peak signal-to-noise ratio (SNR) and signal-to-noise-plus-distortion ratio (SNDR) of 58.4 dB and 56.5 dB, respectively, and differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.48/+0.58 LSB and plusmn1 LSB, respectively, with a power dissipation of 50 mW (including analog, digital, and clock generator power) from a 2.5 V supply (1.2 V for the digital section), giving a per-channel power dissipation of 25 mW.     

A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration

This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-$mu{hbox {m}}$ CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within $pm 0.30$ LSB and $pm 0.95$ LSB, respectively. The ADC occupies an active die area of $0.56~{hbox {mm}}^{2}$ and consumes 51.6 mW at a 1.2 V power supply.      

An 8-bit 80-Msample/s pipelined analog-to-digital converter withbackground calibration

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm ² in a single-poly 0.5 μm CMOS technology     

基于码密度统计的流水线模数转换器校准算法研究

本文提出了一种用于校准流水线模数转换器线性误差的数字后台校准算法。该算法不需要修改转换器级电路部分,只需要一部分用于统计模数转换器输出码的数字电路即可完成。通过分析流水线模数转换器输出的数字码,该算法可以计算出每一级级电路对应的权重。本文利用一个14位的流水线模数转换器来验证该算法。测试结果显示,转换器的积分非线性由90LSB下降到0.8LSB,微分非线性由2LSB下降到0.3LSB;信噪失真比从38dB提高到66.5dB,总谐波失真从-37dB下降到-80dB。转换器的线性度有很大提高。     

An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

An 8-b 100-MS/s pipelined analog-to-digital converter(ADC) is presented.Without the dedicated sample-and -hold amplifier(SHA),it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the...     

A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10^-11 at 4 GS/s.     

一个高线性13位流水线CMOS A/D转换器

介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性,自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现,包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试,得到的微分非线性为-0.18/0.15LSB,积分非线性为-0.35/0.5LSB,信号与噪声加失真比(SNDR)为75.7dB,无杂散动态范围(SFDR)为90.5dBc;在5MHz采样时钟和2.4MHz输入信号下测试,得到的SNDR和SFDR分别为73.7dB和83.9dBc.所有测试均在2.7V电源下进行,对应于采样率为2.5MS/s和5Ms/s的功耗(包括焊盘驱动电路)分别为21mW和34mW.     

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.     

Digital background calibration of charge pump based pipelined ADC

In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.