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1.
The thermal shock resistance of miniaturized multilayer ceramic capacitors (MLCs), of sizes 0402, 0603, 0805 and 1206, was investigated by comparing the leakage currents before and after thermal shock. It was generally found that smaller capacitors have a higher thermal shock resistance than larger ones. The 0402 MLC possesses a thermal shock resistance in excess of 420 C. The linear interdependence of thermal shock resistance and reciprocal of half thickness, as predicted by conventional thermal shock analysis, was not observed. Instead, the thermal shock resistance of an MLC was found to be inversely proportional to the total area of its ceramic surface. This confirms that pre-existing flaws on the ceramic surface dominate the crack initiation process and are therefore primarily responsible for determining the thermal shock resistance of an MLC.  相似文献   

2.
Surface mount technology is used widely nowadays in the manufacture of printed circuit board assemblies in the electronics industry. The occurrence of defective products when this technology is used is mostly caused by technological problems, but sometimes it is also caused by management problems or human errors. When technological problems are being tackled, human interactions will always be involved. This is because the quality of a product is related to the quality of the material, the design of the product and the manufacturing process, and as tasks are subdivided, problems occurring in production cannot be solved completely by the sole effort of a single individual. Hence improvement of product quality involes man, machine, and material. This article explains how quality problems arising from surface mount technology are tackled by team effort in an organization via the implementation of a process-oriented total quality control system.  相似文献   

3.
Results of sintering multilayer ceramic capacitors by a high-frequency field are presented. It is shown that half-finished multilayer ceramic capacitors subjected to a high-frequency field are sintered in 5–15 min instead of the several hours taken in the conventional method. Possibilities of using high-frequency fields for sintering ceramic materials and electronic products are discussed.Vitebsk Branch of the Institute of Solid State and Semiconductor Physics, Academy of Sciences of Belarus, Vitebsk, Belarus. Translated from Inzhenerno-Fizicheskii Zhurnal, Vol. 68, No. 1, pp. 143–145, January–February, 1995.  相似文献   

4.
采用新型功能添加剂,在缩短硫化时间避免涂膜难干或发粘的同时,解决了体系储存稳定性下降的问题;选择使用阻燃剂,有效提高其阻燃性并赋予涂覆膜自熄性,且保证涂膜原有的透明性;最终成功制备出透明保形涂覆液.涂覆液固化时间短(20min内完全表干),涂膜具有良好的粘附力且阻燃性好(氧指数为49%),介电强度高(37kV/mm),完全可以满足实际电路板涂覆生产线要求.  相似文献   

5.
Characterization of the mechanical properties of small components is a significant issue. For the multilayer ceramic capacitor (MLCC), direct loading by conventional facilities is not suitable because of its small size. To date, the standard method used to determine MLCC’s mechanical properties is board flex test; i.e., mounting the capacitor onto a printed circuit board (PCB) and applying bending to the entire system. Failure is defined as cracking or capacitance loss of the MLCC when the mounted PCB is subjected to a specified deflection, and the measurements are usually performed after the test. In this case, characterization of the mechanical properties of MLCCs is qualitative. The purpose of the present study was to quantitatively characterize the mechanical properties of MLCCs. Specifically, the acoustic emission was used to detect cracking of MLCCs during the board flex test. To confirm cracking-induced acoustic emission, telemicroscope was used to perform the in situ observation of cracking. Finite element analyses were also performed to analyze the stress field resulting from the test to compare with the observed cracking path. In addition, nanoindentation was used to explore the mechanical properties of the constituents of MLCCs in the nanoscale. Our work not only allows identification and understanding of the fracture origin, but also provides guidelines in the material design.  相似文献   

6.
In the usage of multilayer ceramic capacitors, we are concerned with the intrinsic dielectric properties of the ceramic and its long-term stability/reliability under external stresses in service conditions. Of equal importance to long-term reliability is the short-term survivability under current (power)-surge conditions. It differs from the ability to withstand voltage surge, which is determined by the dielectric strength of the ceramic. In this paper, we present some observations on sectioned and polished multilayer ceramic capacitors, which were subjected to controlled current-surge test conditions. Capacitors from several vendors were examined. The samples were examinedin situ under an optical microscope while current pulses of varying magnitude were applied at a constant voltage. Subsequently some samples were further examined by scanning electron microscopy. The failure mechanism appeared to be the heat-induced local melting of internal electrodes, which might then lead to a blow-out or charring of the capacitor. In less severe cases, we observed local melting and crack formation in the surrounding ceramic as well. The primary change in capacitor properties was in the degradation of the insulation resistance. In severe cases, this also led to an increase in the dissipation factor.  相似文献   

7.
This paper reports on research which examined the use of statistical process control (SPC) in the quality improvement process of a printed circuit board (PCB) manufacturer. The implementation of SPC is discussed along with the difficulties encountered and benefits achieved. The findings indicate that SPC is a tool which can be of considerable assistance in the quality improvement process of PCB manufacture. However, the variety of manufacturing technologies used and the number of interconnecting processes makes the application of SPC more difficult than in other traditional industries. The lessons learned include that the introduction of SPC must not be rushed, that discipline and support from all levels in the organization are crucial to its success, that SPC cannot be used in isolation—it needs the structure of a continuous improvement initiative, and that getting processes in a state of statistical control and capable, and keeping them there, is a difficult task which involves considerable effort and patience.  相似文献   

8.
9.
The problem of workload planning in small lot printed circuit board (PCB) assembly concerns the determination of the daily mix of production orders to be released into the production system. When switching from one production order (board type) to another, a considerable set-up time is incurred based on the number of component feeders to be replaced in the component magazine of the assembly machines. To support the order-mix decision faced by a major electronics manufacturer, two versions of a linear programming model are developed. The models differ primarily in their degree of aggregation and their computational effort. In order to reduce the aggregational error incurred, a fuzzy approach is developed to estimate the number of component set-ups at automatic SMD placement machines. Our numerical investigation reveals that sufficiently accurate solutions may be obtained from a highly aggregate fuzzy LP-model and this is achieved with considerably less computational effort than with a more detailed LP-model. We also demonstrate the potential suitability of the fuzzy LP-model for implementation within an interactive decision support system.  相似文献   

10.
Component placement sequencing is a challenging problem that arises in automated assembly of printed circuit boards. While for some placement machines all placement sequences are acceptable, in other cases some sequences are not allowed because of the shape of the placement head. In such cases, while the head moves down to perform a placement, it might damage a previously placed component, and the problem of determining a minimum cost and at the same time acceptable sequence leads to a Precedence Constrained Travelling Salesman Problem formulation. In this study, a solution procedure to such a formulation is developed and its implementation in a real PCB assembly environment is discussed.  相似文献   

11.
Product design and fabrication constitute an important business activity in any manufacturing firm. Designing an optimized product fabrication process is an important problem in itself and is of significant practical and research interest. In this paper, we look into a printed circuit board (PCB) fabrication process and investigate ways in which the fabrication cycle time can be minimized. Single class queueing networks constitute the modelling framework for our study. The model developed in this paper and the analysis experiments carried out are based on extensive data collected on a PCB fabrication company located in Bangalore, India. This is a representative PCB fabrication company involving multiple, concurrent fabrication works with contention for human/technical resources. Our model seeks to capture faithfully the flow of the fabrication process in this company and such other organisations, using queueing networks. Using the model developed, we explore how the cycle times can be reduced using input control, load balancing, and variability reduction. The model presented is sufficiently generic and conceptual; its scope extends beyond that of a PCB fabrication organization.  相似文献   

12.
We establish a systematic methodology to design and analyse electromagnetic components such as advanced multilayer ceramic capacitors (MLCCs) using the finite element (FE) method. We employ a coupled formulation to compute the interaction between the electric and magnetic fields. Unlike a linear distribution of current assumed in the circuit model, an accurate electrostatic solution to model the entire advanced MLCCs (4 × 4 × 27 = 432 cells) is presented. The FE solution is used to compute the lumped parameters for a range of frequencies. These lumped parameters are then used to compute the parasitic elements of the MLCCs. We introduce two algorithms to efficiently analyse the behaviour of a capacitor with changing frequency. The lower frequency (much below the self‐resonant frequency of the capacitor) algorithm separates the effect of the electric and magnetic fields and reduces the computational effort required to solve the FE problem, whereas, the high‐frequency algorithm couples the effect between the electric and the magnetic fields. We use these algorithms in conjunction with a new multiple scale technique to effectively determine the small values of R, L and C in MLCCs. The formulation, the implementation, and the numerical results demonstrate the efficacy of the present FE formulation and establish a systematic methodology to design and analyse advanced electromagnetic components. Copyright © 2003 John Wiley & Sons, Ltd.  相似文献   

13.
An approach to minimize makespan for assigning boards to production lines is described. Because of sequence-dependent set-up times, board assignment and component allocation have to be performed concurrently. An integrated methodology is developed to obtain a solution to these two problems. The methodology consists of seven phases: printed circuit board grouping, family decomposition, subfamily sequencing, Keep Tool Needed Soonest (KTNS) procedure, component set-up determination, component allocation and board assignment. Application of the methodology to industrial problems demonstrates that it can solve large-scale problems efficiently. In addition, the effect of two key parameters, feeder capacity and threshold value, on the performance of the solution procedure was examined. The results indicate that feeder capacity has an impact on total workload imbalance but not on the global makespan. Threshold value, a measure of effectiveness of joining a component type to a component group for a printed circuit board family, has a significant effect on the global makespan. The interactions of threshold value, and variations in printed circuit board requirement and component usage also affect global makespan.  相似文献   

14.
We consider an operation assignment problem arising from a Printed Circuit (PC) board assembly process. The research was inspired by applications at Hewlett-Packard Company where hundreds of types of PC boards require the insertion of thousands of types of components. The components can be inserted manually or by automated insertion machines. The machines can only hold a limited number of different component types. We investigate how to assign the boards and components to the machines and manual process so as to minimize cost while at the same time balancing machine workloads. We first present a Binary Integer Program (BIP) formulation of the problem. We then develop optimality results that allow us to reduce significantly the size of the BIP. Using the improved BIP formulation, and upper bounds generated using a Cost Minimizing Workload Balancing (CMWB) heuristic that we develop, we show how branch-and-bound can be used to find optimal solutions to small and medium-sized problems in reasonable time. We also show that the CMWB heuristic finds solutions in seconds of CPU time that are within a few percent of optimal. In addition, the CMWB heuristic outperforms the heuristic that has been used at Hewlett-Packard, as well as the longest expected processing time heuristic. Although this paper specifically addresses a problem of partially-automated PC board assembly, the results apply to a more general set of problems, including job and tool assignment in flexible manufacturing systems, and general operation assignment problems.  相似文献   

15.
The rapid growth in printed circuit board production has led to the growing importance of microdrilling. Owing to the trend for high-density circuits on printed circuit boards, the diameter of a microdrill has to be much finer than ever before. The inspection for microdrills becomes more difficult and the detection of defects is harder. An automated visual inspection scheme for detecting the major defects of microdrills is proposed. The colour images of microdrills are first derived, and the boundary of the lip relief plane is extracted. A robust K-curvature corner detection algorithm is then used to detect the corners on the blade boundaries and to split boundaries into segments. The least-squares linear regression method is used to fit the segments into linear equations. With the fitted equations, the intersections on the boundaries of two facets are located and their distances (gap or overlap) are measured. In addition, the defects of taper and flare are identified by comparing the angle measurements with predefined specifications. Two types of microdrills are used to verify the proposed inspection process. Experimental results show that the proposed scheme reliably achieves precise inspection.  相似文献   

16.
In this paper we present a comparison between two non-destructive techniques for crack detection in MLCCs. First, if a type II MLCC is biased with a DC field, the capacitor becomes temporarily ‘poled’ and can act as a transducer. This is induced by a residual piezoelectric effect used in the impedance spectroscopy method. Second, we used a scanning ultrasonic system working in the 10–100 MHz frequency bandwidth. To understand the ultrasonic signature, we used time-of-flight (TOF) detection with short-time Fourier transform (STFT) analysis to determine the depth and nature of defects with high accuracy. An application of digital signal processing to the characterization of defects is presented for a lot of MLCCs with cracks defects. For comparison, the same lot was tested with the piezoelectric method. The two techniques are closely correlated. © 1998 John Wiley & Sons, Ltd.  相似文献   

17.
This paper is concerned with constructing a high-G drop impact test condition for investigating the impact-induced failure phenomenon of the solder ball array located in the chip packaged printed circuit board. An impact environment satisfying the JEDEC B service conditions, requiring a 0.5 ms half-sine impact pulse duration with a peak acceleration at 1500 G, were constructed using an instrumented drop tower tester. Fifteen wafer-level CSP chips were installed on a standard printed circuit board (PCB) with a dimension of 132×77×1 mm3. A number of these chip packaged PCB bonded with four different compositions of solder joints with or without lead using the surface-mounted technology (SMT) were studied. During the drop impact tests, the chip packaged PCB circuit was monitored using the multi-event detector system (ETAC) to examine whether circuit fails or not. In addition, the drop impact dynamic response of the PCB and the acceleration at the prescribed location of the drop table were recorded and analyzed. Transient stress responses in the solder joints were provided using the LS-DYNA explicit code. Numerically predicted failure locations of the solder joints are close to those observed from actual drop impact experiments.  相似文献   

18.
Jeonghoon Mo 《工程优选》2017,49(10):1750-1760
In this article, the problems of test sequence generation and scheduling optimization for a tester with parallel devices are considered in order to reduce inspection times. Two optimization problems are formulated for test sequence generation and the scheduling of parallel devices, and then algorithms to address these problems are proposed. The proposed algorithms were tested via simulation and experiments. The test results show two to four times improvement over existing methods.  相似文献   

19.
High reliability multilayer ceramic chip capacitors are necessary for use in surface mounting processes which are more mechanically and thermally severe than the traditional through-hole processes. Moreover, in specific environments, even a small defect can be considered as catastrophic for the working of the electronic circuit or even of the entire system. In order to look for the failures—intrinsic latent defects and those caused by SMT soldering processes—appearing in these components, many techniques of analysis can be used. With this present work, we focus on one technique based on the principle of electromechanical resonances existing in piezoelectric materials under a d.c. bias field. The free correlation between the impedance measurement of the chip under a sufficient voltage allows us to highlight some conclusions concerning the behaviour, the nature of the defects and the long-term reliability of ceramic chip capacitors. This method has the advantage of being non-destructive, rapid, efficient and low-cost.  相似文献   

20.
Considering the growing concerns and importance of environmental issues, manufacturing industrialists, in particular those in electronics manufacturing, are seeking methods to evaluate the environmental performance of their manufacturing processes. These environmental evaluation tools should be capable of performing detailed analysis on the environmental performance of each individual process unit, identifying the environmental improvement opportunity and providing adequate decision support to environmental engineers for process modification and operational change. This paper modifies and improves the environmental impact evaluation model already developed and provides directions for decision-making at various stages of the analysis. The decision algorithm in this revised model adopts a hierarchical environmental impact evaluation approach and uses five impact categories related to ecological health and seven categories related to human health to form the base of an evaluation hierarchy. The algorithm, with its evaluation results presented in all levels of the hierarchy, is proposed as a means of tracking, controlling and improving the environmental performance of a process. A printed circuit board case study shows the effectiveness and applicability of the algorithm. The results indicate that the electroless copper process has a higher impact on ecological health than on human health, and that the phosphoric acid in the waste components is the identified major source of the impact on ecological health.  相似文献   

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