A 1.5-V 550-/spl mu/W 176/spl times/144 autonomous CMOS active pixel image sensor

This paper addresses the development of a micropower 176/spl times/144 CMOS active pixel image sensor that dissipates one to two orders of magnitude less power than current state-of-the-art CMOS image sensors. The chip operates from a 1.5-V voltage source and the power consumption measured for the chip running from an internal 25.2-MHz clock yielding 30 frames per second is about 550 /spl mu/W. This amount enables the sensor to run from a watch battery. In order to achieve design goals, a low-power sensor design methodology is applied throughout the design process from system-level to process-level, while realizing the performance to satisfy the design specification. As an autonomous sensor, it can be operated with only three pads [GND, VDD (1.2-1.7 V), DATAOUT]. The die occupies 4 mm/sup 2/ of silicon.     

A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

This paper describes a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20/spl times/20 mm with a 7-/spl mu/m pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization.     

A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor

The ultrahigh-definition television (UDTV) camera system requires an image sensor having four times higher resolution and two times higher frame rate than the conventional HDTV systems. Also, an image sensor with a small optical format and low power consumption is required for practical UDTV camera systems. To respond to these requirements, we have developed an 8.3-M-pixel digital-output CMOS active pixel sensor (APS) for the UDTV application. It features an optical format of 1.25inch, low power consumption of less than 600 mW at dark, while reproducing a low-noise, 60-frames/s progressive scan image. The image sensor is equipped with 1920 on-chip 10-bit analog-to-digital converters and outputs digital data stream through 16 parallel output ports. Design considerations to reproduce a low-noise, high-resolution image at high frame rate of 60 fps are described. Implementation and experimental results of the 8.3-M-pixel CMOS APS are presented.     

A CMOS 1/spl times/-16/spl times/ speed DVD write channel IC

Optical recording demands a meticulous write strategy to control the laser beam power and regulate the phase change layer temperature tightly. The width, height, and delay of a string of short pulses applied to the laser diode need to be adjusted in fine steps, and the writing speed varies widely per applications. A multi-phase phase-locked loop (PLL) tracks a wide range of clock frequencies, and provides a low-jitter time base for write pulses. With two enabling circuit concepts, PLL loop filter voltage folding/unfolding and switch-in of parallel MOS resistors in delay cells, it is possible to operate a PLL to cover a frequency range spanning over three octaves with one VCO. A 10-stage differential VCO is phase-locked to the input channel clock ranging from 26 to 420 MHz (1/spl times/-16/spl times/ DVD speed), and its 20-phase outputs are used to generate write pulses. The pulsewidth and delay are programmed with 120 /spl plusmn/ 40 ps time resolution. The prototype chip fabricated in 0.35 /spl mu/m CMOS occupies 3.5/spl times/3.3 mm/sup 2/, and consumes 294 mW at 3.3 V.     

A 0.7-V MOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator in standard digital CMOS technology

A 0.7-V MOSFET-only /spl Sigma//spl Delta/ modulator for voice band applications is presented. The second-order modulator is realized using a switched-opamp technique. All capacitors are realized using compensated MOS devices operated in the depletion region. A combination of parallel and series compensated depletion-mode MOSCAPs is used to obtain high area efficiency. The circuit is fabricated in a 0.18-/spl mu/m CMOS process. The only components used are standard n-MOS and p-MOS transistors with threshold voltages of approximately 400 mV. All transistors are operated within the supply voltage window of 0.7 V; voltage boosting techniques are not used. The active area is 0.082 mm/sup 2/. The modulator achieves 67-dB signal-to-noise-and-distortion ratio, 70-dB signal-to-noise ratio, and 75-dB dynamic range at 8-kHz signal bandwidth and consumes 80 /spl mu/W of power.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.     

Highly linear 2.5-V CMOS /spl Sigma//spl Delta/ modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

A 24/spl times/6 interlaced-scan MOS image sensor

A new 24/spl times/6 self-scanned MOS image sensor has been developed for the Optacon reading aid for the blind. This new image sensor has a unique circuit design that provides in a simple manner interlaced row scanning and low-light level detection. While a previous investigation (1969) showed that self-scanned MOS image sensors are capable of operating with illumination levels of 1 /spl mu/W/cm/SUP 2/, this report presents a working circuit to simply realize this performance in a device compatible with a reading aid application. The previous investigation also did not consider the noise at high-scanning frequencies (175 kHz) associated with package interconnection capacitances. This new circuit attempts to minimize this previously neglected switching noise.     

A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

A high-voltage output driver in a 2.5-V 0.25-/spl mu/m CMOS technology

The design of a high-voltage output driver in a digital 0.25-/spl mu/m 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-/spl Omega/ load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 /spl Omega/.     

A 16 ns 2K/spl times/8 bit full CMOS SRAM

A high-speed 2K/spl times/8 bit full CMOS SRAM fabricated with a platinum silicide gate electrode and single-level aluminum technology is described. A typical address access time of 16 ns, which is comparable to the 16-kb bipolar SRAMs, was achieved. Typical active and standby power dissipations are 150 mW and 25 nW, respectively. The platinum silicide word line reduces the total address access time by 25%. A compact cell layout design, as well as a 1.5-/spl mu/m device feature size, also gives fast access time. The properly controlled bit line swing voltage provides reliable and fast readout operation. The chip size of the SRAM is 2.7/spl times/3.5 mm.     

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.     

An 18 ns 4K/spl times/4 CMOS SRAM

A high-speed 11-mm/SUP 2/ 4K/spl times/4 CMOS static RAM fabricated developed. This circuit uses improved circuit techniques to with a single-polysilicon, single-metal process has been obtain a typical 18-ns access time with only 250 mW of active power. Among the topics discussed are the smallest single-polysilicon static RAM cell reported to date; the use of address transition assistance for equalization and boosting; a short-delay, positive-feedback boosted word line; high-speed predecoded row and column decoders; new fully compensated bit-line loads and column presence amps; and an easily implemented redundancy scheme using laser fusing techniques.     

A high-speed 64K/spl times/4 CMOS DRAM using on-chip self-timing techniques

The duration of internal operation of this DRAM is controlled by on-chip self-timing signals. With this feature, the leading and trailing edges of the row address strobe are allowed to have timing windows of 16 and 11 ns, respectively, even at a minimum cycle time of 80 ns. A novel address decoding scheme, utilizing a combination of NMOS NOR row decoders, CMOS NAND column decoders, and common predecoders, is employed to realize a fast array access time and a small die. The RAM has been fabricated with a 1.2-/spl mu/m n-well CMOS technology, and has a 21.34-mm/SUP 2/ die. Typical row access and column address access times are 47 and 16 ns, respectively. The active power dissipation is 115 mW at 200-ns cycle time.     

A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder

This paper describes a 4-state rate-1/2 analog convolutional decoder fabricated in 0.8-μm CMOS technology. Although analog implementations have been described in the literature, this decoder is the first to be reported realizing the add-compare-select section entirely with current-mode analog circuits. It operates at data rates up to 115 Mb/s (channel rate 230 Mb/s) and consumes 39 mW at that rate from a single 2.8-V power supply. At a rate of 100 Mb/s, the power consumption per trellis state is about 1/3 that of a comparable digital system. In addition, at 50 Mb/s (the only rate at which comparative data were available), the power consumption per trellis state is similarly about 1/3 that of the best competing analog realization (i.e., excluding, for example, PR4 detectors which use a simplified form of the Viterbi algorithm). The chip contains 3.7 K transistors of which less than 1 K are used in the analog part of the decoder. The die has a core area of 1 mm², of which about 1/3 contains the analog section. The measured performance is close to that of an ideal Viterbi decoder with infinite quantization. In addition, a technique is described which extends the application of the circuits to decoders with a larger number of states. A typical example is a 64-state decoder for use in high-speed satellite communications     

A 1.8-V 2.4/5.15-GHz dual-band LCVCO in 0.18-/spl mu/m CMOS technology

A dual band, fully integrated, low phase-noise and low-power LC voltage-controlled oscillator (VCO) operating at the 2.4-GHz industrial scientific and medical band and 5.15-GHz unlicensed national information infrastructure band has been demonstrated in an 0.18-/spl mu/m CMOS process. At 1.8-V power supply voltage, the power dissipation is only 5.4mW for a 2.4-GHz band and 8mW for a 5.15-GHz band. The proposed VCO features phase-noise of -135dBc/Hz at 3-MHz offset frequency away from the carrier frequency of 2.74GHz and -126dBc/Hz at 3-MHz offset frequency away from 5.49GHz. The oscillator is tuned from 2.2 to 2.85GHz in the low band (2.4-GHz band) and from 4.4 to 5.7GHz in the high band (5.15-GHz band).     

A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC

CMOS analog-to-digital converters (ADC's) require either bootstrapping techniques or low-threshold devices to function at low supply voltages. A 6-b 50-MSamples/s ADC in normal-threshold CMOS operates with a single battery cell as low as 0.9 V without bootstrapping. A current-interpolation approach is taken to configure a 1-V ADC system that does not allow more than one V_GS plus one V_DSsat between the supply rails. The prototype takes a rail-to-rail input and works with a single system clock. The chip fabricated in 0.35-μm CMOS occupies an area of 2.4×2 mm² and consumes 10 mW each in analog and digital supplies