用直接隧道栅电流在线表征PMOSFET负偏压温度不稳定性

本文提出了一种在线表征负偏压温度不稳定性(NBTI,negative bias temperature insta-bility)退化的方法--直接隧道栅电流表征法(DTGCM,DT Gate Current Method)。用这种方法可以得到NBTI应力诱生在超薄栅氧化层中的缺陷密度(包括氧化层体陷阱密度和界面态密度),并得到PMOSFET器件阈值电压的漂移(ΔVth)信息。这种方法可以有效避免NBTI恢复效应的影响。     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具.     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

FN应力下超薄栅N-MOSFET失效的统计特征及寿命预测

通过对不同氧化层厚度的N-MOSFET在各种条件下加速寿命实验的研究,发现栅电压漂移符合Weibull分布.Weibull分布统计分析表明,5.0、7.0和9.0nm器件在27和105C下本征失效的形状因子相同,即本征失效的失效机制在高低温度下相同.非本征失效的比例随温度升高而增大.在此基础上得出平均寿命(t50)与加速电场E成指数关系,进而提出了器件的寿命预测方法.此方法可预测超薄栅N-MOSFET在FN应力下的寿命.     

FN应力下超薄栅N-MOSFET失效的统计特征及寿命预测

通过对不同氧化层厚度的 N- MOSFET在各种条件下加速寿命实验的研究 ,发现栅电压漂移符合 Weibull分布 . Weibull分布统计分析表明 ,5 .0、 7.0和 9.0 nm器件在 2 7和 10 5℃下本征失效的形状因子相同 ,即本征失效的失效机制在高低温度下相同 .非本征失效的比例随温度升高而增大 .在此基础上得出平均寿命 (t50 )与加速电场E成指数关系 ,进而提出了器件的寿命预测方法 .此方法可预测超薄栅 N- MOSFET在 FN应力下的寿命     

低电场应力下闪速存储器的退化特性

基于负栅源边擦除的闪速存储器存储单元,研究了形成应力诱生漏电流的三种导电机制,同时采用新的实验方法对引起瞬态和稳态电流的电压漂移量进行了测量.并利用电容耦合效应模型对闪速存储器存储单元的可靠性进行了研究,结果表明,在低电场应力下,其可靠性问题主要由载流子在氧化层里充放电引起.     

低电场应力下闪速存储器的退化特性

基于负栅源边擦除的闪速存储器存储单元,研究了形成应力诱生漏电流的三种导电机制,同时采用新的实验方法对引起瞬态和稳态电流的电压漂移量进行了测量.并利用电容耦合效应模型对闪速存储器存储单元的可靠性进行了研究,结果表明,在低电场应力下,其可靠性问题主要由载流子在氧化层里充放电引起.     

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of 0.036 decade/°C.     

Impacts of the recovery phenomena on the worst-case of damage in DC/AC stressed ultra-thin NO gate-oxide MOSFETs

Permanent damage induced by Channel Hot-Carrier (CHC) injections have been distinguished from the charge–discharge of near-interface traps in ultra-thin gate-oxide (1.6 nm) MOSFETs. It is shown that usual DC accelerating techniques mostly devoted to CHC damage at large voltage conditions cannot be used alone for low supply voltage (V_DD = 1V) MOSFETs. This arises from the charging of slow traps which induces a worst-case of damage which is relaxing in different ways depending on the discharging bias and cold phases. This is particularly more severe under hole injections in P-channel than under electron injections in N-channel MOSFETs in relation to the smaller mobility of holes and to the gate-oxide nitridation which induces deep traps from the oxide valence band. The true effects of the distinct damage and relaxations are further analysed using AC stresses which are required for the worst-case determination in advanced logic circuits. This is further evidenced by the determination of the effective quasi-static time factors dependent on the alternated damaging, discharging, and relaxing periods involved in ultra-thin gate-oxide MOSFETs operating at low voltage.     

The charging and discharging of high-voltage stress-generated trapsin thin silicon oxide

Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide     

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.     

A Modified Charge Pumping Method for Measuring Interface States Up to the Ghz Range

In this paper we present a modified on-chip charge pumping method for measuring the interface states in ultra-thin gate oxide complementary metal-oxide-semiconductor (CMOS) technology. The proposed method, which characterizes oxide interface states by applying pulse frequencies up to the GHz range, is used to evaluate the evolution of interface states due to dynamic negative bias temperature instability stress on the p-channel field-effect transistor (pFET). The results show that charge pumping increases linearly at frequencies up to the GHz range and that the time dependence of interface states due to AC negative bias temperature instability (NBTI) stress increases with a power law distribution. In addition, we demonstrate experimentally that the V_TH shift due to AC NBTI stress depends on interface states and oxide traps.     

The effect of change of voltage acceleration on temperatureactivation of oxide breakdown for ultrathin oxides

We report the effect of change of voltage acceleration on temperature dependence of oxide breakdown for ultra-thin oxides below 6 nm. The time- or charge-to-breakdown (T_BD/Q_BD) is directly measured over a wide range of temperatures (-30°C to 200°C) for several fixed voltages using different area capacitors and long-term stress. Using extensive experimental evidence, we unequivocally demonstrate that this strong temperature dependence of oxide breakdown on ultra-thin oxides is not a thickness effect as previously suggested at least for thickness range investigated in this work. It is a consequence of two experimental facts: 1) voltage-dependent voltage acceleration and 2) temperature-independent voltage acceleration within a fixed T_BD window. These results provide a coherent picture for T_BD in both voltage and temperature domains for ultra-thin oxides     

The effect of a post processing thermal anneal on pre-existing and stress induced electrically active defects in ultra-thin SiON dielectric layers

In this work we demonstrate the effects of a post processing high temperature anneal on the reliability of ultra-thin SiON layers fabricated into both nmos and pmos devices in terms of the initial gate leakage current, stress induced leakage current (SILC), and the time dependent dielectric breakdown behaviour. The devices under consideration were annealed at several temperatures up to 500 °C. We show that different mechanisms dominate the leakage behaviour at different temperatures by examining the relative leakage in the low voltage range. In particular for pmos devices, the emptying of electron traps induced by temperature and subsequent annealing of these traps alters the leakage current profiles significantly, dependent on anneal temperature. We show that annealing improves the time dependent dielectric breakdown (TDDB) lifetimes of nmos devices and examine the reasons for this.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Linear cofactor difference method of MOSFET subthresholdcharacteristics for extracting interface traps induced by gate oxidestress test

A new subthreshold analysis technique, the linear cofactor difference method, is presented in this brief for extraction of the MOSFET interface traps induced by the gate oxide stress test. This technique relies on new linear cofactor difference extreme spectral characteristics of MOSFET gate voltage in the subthreshold region. It is shown that this method enables reliable extraction of the increased interface traps with a rise of the accumulated gate oxide stress test time to be obtained and that its validity is also verified by the extraction experiments on an n-channel MOSFET (nMOST) device