Relationship between texture and electromigration lifetime in sputtered AI-1% Si thin films

The relationship among the grain structure, texture, and electromigration lifetime of four Al-1% silicon metallizations produced under similar sputtering conditions was explored. The grain sizes and distributions were similar and the grain structure was near-bamboo for all metallizations. All metallizations exhibited a near-(111) fiber texture, as determined by the pole figure technique. Differences in electromigration behavior were noted. Three of the metallizations exhibited a bimodal failure distribution while the fourth was monomodal and had the longest electromigration lifetime. The electromigration lifetime was directly related to the strength of the (111) fiber texture in the metallization as anticipated. However, whereas the grain size distribution has an effect on the electromigration lifetime when metallization lines are several grains wide, the electromigration lifetime of these near-bamboo metallizations appeared independent of the grain structure. It was also observed that a number of failures occurred in the 8 μm interconnect supplying the 5 μm wide test lines. This apparently reflects an increased susceptibility of the wider interconnect lines to electromigration damage.     

Copper interconnection lines: SARF characterization and lifetime test

Copper thin films have been deposited onto silicon substrates by means of two different deposition techniques, resulting in metallizations with different microstructure. In particular, transmission electron microscopy (TEM) observations have shown that the two types of films are characterized by different distributions of the grain size. Lifetime and SARF (Spectral Analysis of Resistance Fluctuations) tests have been performed on lines obtained from the two metallizations in order to compare their resistance to electromigration. The results of the tests confirm those already obtained in A1 based lines; in fact, a clear correlation exists among the average grain size, the lifetime and the level of electromigration noise.     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

A polysilicon source and drain MOS transistor (PSD MOST)

An MOS transistor is described in which the source and drain areas are obtained by diffusion from doped polycrystalline silicon. Polysilicon tracks form the interconnect with the diffusion areas without the need for contact windows. As a result transistor and junction sizes are reduced by a factor 2 or 3 over a normal structure. Polycrystalline silicon tracks in this new technique are of greater advantage as interconnect layers than in the silicon gate tecgnique.     

Ion beam preparation of passivated copper integrated circuit structures for electron backscatter diffraction/orientation imaging microscopy analysis

Passivation layers were removed from copper interconnect lines using a broad beam ion source in preparation for electron backscatter diffraction (EBSD) and orientation imaging microscopy (OIM) analysis. Results were obtained on interconnect lines with widths as small as 0.25 μm. The effects of ion beam energy and scanning electron microscope (SEM) acceleration voltage on the quality of the results obtained are examined and explained. The use of thin amorphous carbon coatings to reduce specimen charging during orientation data collection is also discussed.     

Texture investigation of copper interconnects with a different line width

To understand the effect of line width on textural and microstructural evolution of Cu damascene interconnect, three Cu interconnects samples with different line widths are investigated. According to x-ray diffraction (XRD) results, the (111) texture is developed in all investigated lines. Scattered {111}〈112〉 and {111}〈110〉 texture components are present in 0.18-μm-width interconnect lines, and the {111}〈110〉 texture was developed in 2-μm-width interconnect lines. The directional changes of the (111) plane orientation with increased line width were investigated by XRD. In addition, microstructure and grain-boundary character distribution (GBCD) of Cu interconnect were measured using electron backscattered diffraction (EBSD) techniques. This measurement demonstrated that a bamboo-like microstructure is developed in the narrow line, and a polygranular structure is developed in the wider line. The fraction of ∑3 boundaries is increased as the line width increases but is decreased in the blanket film. A new interpretation of textural evolution in damascene interconnect lines after annealing is suggested, based on the state of stress and growth mechanisms of Cu deposits.     

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

Sem,auger spectroscopy and ion backscattering techniques applied to analyses of Au/refractory metallizations

The concurrent application of the SEM, AES, X-ray diffractometry and Rutherford Backscattering (RBS) techniques to Au/refractory metallizations is analyzed with respect to the study of thin film interdiffusion, intermetallic formation, microcracking and oxidation phenomena. The SEM in the backscatter electron image mode was used for resolution of intermetallic compounds and interdiffusion products, while AES and RBS analyses were used to obtain depth-composition profiles. The metallizations studied were Ta/Pt/Ta/Au and W/Au. The combination of Ta/Pt/Ta and Ti/Pt have been shown to be effective barriers to gold-silicon interdiffusion. Defects in the tungsten barrier were found to result in silicon migration to the front surface and gold migration toward the substrate at temperatures between 550°C-700°C . The diffusion constants for Au-Ta and Au-Pt interdiffusion have been determined from the AES data.     

Si-micromachined coplanar waveguides for use in high-frequencycircuits

This paper describes the development and characterization of a new class of Si-micromachined lines and circuit components for operation between 2-110 GHz. In these lines, which are a finite-ground coplanar-waveguide (FGC) type, Si micromachining is used to remove the dielectric material from the aperture regions in an effort to reduce dispersion and minimize propagation loss. Measured results have shown a considerable loss reduction to levels that compare favorably with those of membrane lines and rectangular waveguides. Micromachined FGC lines have been used to develop V- and W-band bandpass filters. The W-band micromachined FGC filter has shown a 0.8-dB improvement in insertion loss at 94 GHz over a conventional FGC line. This approach offers an excellent alternative to the membrane technology, exhibiting very low loss, no dispersion, and mode-free operation without using membranes to support the interconnect structure     

A novel fast technique for detecting voiding damage in IC interconnects

A novel technique has been developed, which is sensitive to the degree of voiding damage induced in a wide-line interconnect test structure (Testing of conductors, Preliminary Irish patent application, August 26th, 1998). The technique is based on the measurement of the scattering parameters (S-parameters) of a simple, metal-line test structure over a range of high frequencies. The transmission-line parameter, G (leakage conductance), which is calculated from the S-parameter measurements, is shown to be sensitive to distribute voiding, especially in wider lines. This is significant for the following reasons: (1) the measurement is fast — a few seconds per test structure, (2) it can be performed at wafer level, (3) it does not rely on overstressing of the metallization and (4) it is sensitive to the amount of voiding damage present in wide interconnect lines. Potential applications for this technique are: (a) an in-line statistical reliability control (SRC) test for the detection of stress voids induced during processing, and (b) an in-line SRC test for electromigration when preceded by a suitable current pre-stress step.     

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.     

Efficient computation of generalized scattering matrix foranalyzing multilayered periodic structures

An efficient technique is proposed for the computation of the generalized scattering matrix (GSM) of a dielectric interface with periodic metallizations. The technique is based on a spectral domain moment method, but assuming multiple incident Floquet-harmonics and computing the GSM directly. Also, some symmetry properties are exploited, and the whole GSM is computed with similar computer effort as that required for a single scattering coefficient. The technique has been applied to the analysis of periodic surfaces involving rectangular and arbitrarily-shaped metallizations using entire- and sub-domain basis functions, respectively. Losses in both dielectric layers and metallizations have been included in the formulation. Multilayered periodic structures are analyzed in a very flexible and efficient way by cascading iteratively the GSM of each interface with or without metallizations considered as building blocks. Numerical results have been provided for different multilayered structures, and a good agreement with other experimental and theoretical data has been obtained. The proposed technique is very appropriate for the analysis of composite structures when the separation between interfaces is small, and therefore higher-order Floquet-harmonic interaction cannot be neglected     

Direct observation of local strain field for ULSI devices

The in-depth profile of strain distribution from the silicon surface is one of the most important pieces of information for optimizing the device performance. The convergent-beam electron diffraction(CBED) method has been applied to analyze the local strain filed of the active regions for both test structure with the shallow trench isolation(STI) and the conventional LOCOS on a cross-sectional surface. As a result, strain distribution was observed successfully. It was found that the compressive stress exist all over the survey regions. The active region close to the bottom corner of the STI shows a larger stress than that of the conventional LOCOS. It is demonstrated that the CBED technique is very effective for the determination oflocal strain field in a small area of semiconductors and the optimizing of the STI structure andfabrication process.     

Characterization of silicon metallization systems using energetic ion backscattering

Silicon metallization systems have become increasingly sophisticated in order to tailor contact properties such as adhesion, electrical conductivity, barrier height, and long-term reliability. These contact properties are highly susceptible to solid-solid reactions, typically involving atom migration over distances less than 1 µm. Analysis by monoenergetic ion beam irradiation is a valuable new materials characterization technique to optimize process parameters and contact lifetime. Energy analysis of the backscattered ions allows nondestructive determination of the depth distribution of the atomic composition of thin multilayered systems. Recent application of this technique has provided extensive data on the energetics and kinetics of interdiffusion and compound formation for thin-film metallizations on silicon, particularly those used in silicon device technology. After a brief introduction to the technique, the results of these studies are reviewed and systematized. Interdiffusion results are treated for silicon-metal and metal-metal reactions. Distinction is made between cases where internal surface transport effects dominate and cases where compound formation dominates. Examples are taken from each of these areas and are discussed in terms of metallurgical properties.     

Effect of lateral dimensional scaling on the thermal stability of poly-CoSi2 reacted on Si (001)

The effect of lateral dimensional scaling on the thermal stability of polycrystalline cobalt disilicide wires reacted on Si (001) has been studied down to 0.6 μm linewidth. An unpatterned silicide has been used as a reference sample. The annealing processes were performed in N₂ environment, between 900 and 1050°C, on both blanket and patterned silicide. Transmission electron microscopy analyses in plan-view and cross-section allowed us to study the morphology of lines before and after high-temperature processes. Resistance measurements showed a better thermal stability in blanket silicide layer compared to narrow lines. The electrical behaviour of the lines has been explained in terms of both lateral roughness and hole formation in the silicide layer.     

Pt-based metallization of PMOS devices for a compatible monolithic integration of semiconducting/Yba2Cu3O7−δ superconducting devices on silicon

Mo, Pt, Pt/Mo and Pt/Ti thin films have been deposited onto Si and SiO₂ substrates by RF sputtering and annealed in the YBa₂Cu₃O_7−δ (YBCO) growth conditions. The effect of annealing on the sheet resistance of unpatterned layers was measured. A Pt-based multilayered metallization for the PMOS devices was proposed and tested for a compatible monolithic integration of semiconducting devices and YBCO sensors on the same silicon substrate. The best results were obtained with a Pt/Ti/Mo-silicide structure showing 0.472 Ω_□ interconnect sheet resistivity and 2×10⁻⁴ Ω cm² specific contact resistivity after annealing for 60 min at 700 °C in 0.5 mbar O₂ pressure.     

A through-wafer interconnect in silicon for RFICs

In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight. The inductance of vias with nominal aspect ratios between three and 30 approach the theoretically expected values. This interconnect technology was exploited in a novel Faraday cage structure for substrate crosstalk suppression in system-on-chip applications. The isolation structure consists of a ring of grounded vias that surrounds sensitive or noisy portions of a chip. This Faraday cage structure has shown noise suppression of 30 dB at 10 GHz and 16 dB at 50 GHz at a distance of 100 /spl mu/m when compared to the reference structure.     

Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations

We have developed a set of methodologies for thermal aware circuit-level reliability analysis with either Al or Cu metallization in a circuit layout and implemented it in a public domain reliability CAD tool, SysRel. SysRel utilizes a hierarchical reliability analysis flow, with interconnect trees treated as the fundamental reliability unit, that sufficiently captures the differences in electromigration failure between Al and Cu metallizations. Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. Using the best estimates of material parameters and an analytical model, we present a detail comparison of electromigration reliability of a sample test-structure as well as of actual circuit layouts with Al and Cu dual-damascene interconnect systems. We also demonstrate fast thermal-analysis in SysRel for circuit performance driven chip-level reliability assessment.     

超深亚微米高速互连的信号串扰研究

探讨了超深亚微米设计中的高速互连线串扰产生机制,提出了一种描述高速互连串扰的电容、电感耦合模型,通过频域变换方法对模型的有效性进行了理论分析。针对0.18μm工艺条件提出了该模型的测试结构,进行了流片和测量。实测结果表明,该模型能够较好地表征超深亚微米电路的高速互连串扰效应,能够定量计算片上互连线间的耦合串扰,给出不同工艺的互连线长度的优化值。     

50-GHz integrated interconnects in silicon optical microbench technology

A custom-designed silicon-based 50-GHz interconnect is integrated for packaging demonstrations of broadband optoelectronic (OE) applications in silicon optical microbench technology. The half-shielded (or partially shielded) 0.5-cm interconnect has 25-dB isolation and 0.9-dB transmission loss over 50 GHz. When implemented in this packaged architecture, the nature of the interconnect minimizes coupling and eliminates the need for an external test fixture that is prevalent in a more conventional approach. The interconnect is further demonstrated in a multiport electrical package to illustrate the potential of this architecture up to 40-Gb data rates, and the resulting package has insertion loss less than 5 dB at 50 GHz.