LSI/VLSI的任意元胞K行安置的算法

本文提出一种适用于LSI/VLSI任意元胞布局的K行安置的算法。当矩形单元的拓朴位置确定后,每个单元有横放、竖放两个态共有2n个态。在K行安置时,从这2n个态中选出包络矩形面积最小的问题,可归结为求n个态中的包络矩形面积最小,所以是很有效的算法。可以和结群法混合使用;在一定条件下,还可以直接用于准BBL布局。     

通信LSI/VLSI工艺

本文介绍通信LSI/VLSI电路制作技术中目前比较通用的工艺。总的来说,通信电路工艺是以前LSI/VLSI22艺的继续和发展。文中论述的重点是那些和过去LSI/VLSI工艺不同的方面,而这些方面主要体现在模拟电路的制作工艺上。     

通信电路LSI／VLSI发展的新领域

本文介绍了通信技术和通信电路的发展情况,论述了通信技术和通信电路与通信LSI/VLSI发展的密切关系以及通信电路技术的特点;并通过实例说明通信LSI/VLSI中典型的电路和技术。     

AN ALGORITHM FOR VLSI CHANNEL ROUTING USING NEURAL NETWORK

The algorithm for VLSI channel routing using Hopfield neural model is discussed inthis paper.The basic methods of mapping VLSI channel routing problem to Hopfield neural net-work,constructing energy function,setting initial neural status,and selecting various parametersare proposed.Finally,some experimental results are given.     

lambda, an integrated master-slice LSI CAD system

Since 100% routing is essential for master-slice LSI layout design, it is urgently required to establish an integrated CAD system, which significantly reduces the design time. It is almost impossible for even sophisticated automatic programs to accomplish 100% routing without using any man-machine interaction. The lambda system has been developed to achieve complete net connectivity in as short a design time as possible, where efficient automatic procedures are implemented as well as highly interactive functions. The automatic and interactive functions are completely integrated in the system by exploiting human intelligence and the computer's high speed processing.     

LSI版图设计中的一种P／G网布线法

本文提出了一种有效的P/G网布线算法和在积木块式布图系统中实现的策略。与以往算法比较,此算法允许每条电源网具有多个馈电脚存在。其策略包括四个部分:(1)一种有效的层次式自上而下的P/G网平面性分析和拓扑路径分配算法;(2)P/G网线宽的确定;(3)总体压缩和再布线后P/G网布线信息的动态修改;(4)与信号网一起的平面性无网格电源网通道详细嵌入。实验结果表明我们的P/G网布线方法可获得令人满意的布线结果。     

深亚微米条件下的多层VLSI／MCM层分配的遗传算法

本文提出了一个深亚微米条件下的多层ＶＬＳＭＣＭ有约束分层层分配的遗传算法。该算法分为两步：首先进行超层分配，使各线网满足Ｃｒｏｓｓｔａｌｋ约束，且超层数目最少；然后进行各超层的通孔最少化二分层。与目前的层分配算法相比，该遗传算法具有目标全面，全局优化能力强等特点，是一种可应用于深亚微米条件下的ＩＣ ＣＡＤ的有效分层方法。     

LSI版图曝光单元集的算法

本文给出划分一种ＬＳＩ版图设计图形为曝光单元集的一个算法。该算法可同时获正、反两种曝光单元集，为曝光方式的选择提供了灵活性。     

VLSI版图综合中的P／G网实体优化布线

本文提出了一种在通道内将Ｐ／Ｇ网与信号网的实体布线一体化考虑的优化布线策略，目的是在保证１００％布通的前提下，完成Ｐ／Ｇ网的平面化实体嵌入和信号网的实体布线，并使Ｐ／Ｇ走线对信号网走线的影响尽可能小。算法以提高布线区利用率、减小通道高度和减少通孔数为目标，实现总体性能的优化。系统实现的结果表明，本文算法所采用的策略是可行的、有效的。     

AN ELIMINATION ALGORITHM OF EXTREME VALUES FOR INTEGRATED TRISPECTRUM

In this paper,an algorithm for eliminating extreme values and reducing the es-timation variance of an integrated trispectrum under low signal-to -noise ratio and short data sample conditions is presented.An analysis of the results of simulations using this algorithm and comparison with the conventional pewer spectrum and integrated trispectrum methods are presented.     

一种求偶图的所有完备匹配算法

求给定偶图的所有完备匹配问题在LSI/VLSI的布图设计方面有着重要的应用。本文提出了一种求解这一问题的算法。(1)提出了许配树的概念并讨论了其性质;(2)证明了任意一棵许配树T(xi)对应于给定偶图的所有完备匹配的定理;(3)给出了求给定偶图的所有完备匹配的算法。本算法已在BST 386 CAD工作站上用C语言实现。运行结果证明了算法的正确性。算法已作为正在研充的VLSI积木块布图设计系统中的一个模块。     

AN IMPROVED GENETIC ALGORITHM FOR SEARCHING OPTIMAL PARAMETERS IN n-DIMENSIONAL SPACE

An improved genetic algorithm for searching optimal parameters in n-dimensionalspace is presented,which encodes movement direction and distance and searches from coarse toprecise.The algorithm can realize global optimization and improve the search efficiency,and canbe applied effctively in industrial optimization,data mining and pattern recognition.     

VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC

The H.264/AVC Fractional Motion Estimation (FME) with rate-distortion constrained mode decision can improve the rate-distortion efficiency by 2–6 dB in peak signal-to-noise ratio. However, it comes with considerable computation complexity. Acceleration by dedicated hardware is a must for real-time applications. The main difficulty for FME hardware implementation is parallel processing under the constraint of the sequential flow and data dependency. We analyze seven inter-correlative loops extracted from FME procedure and provide decomposing methodologies to obtain efficient projection in hardware implementation. Two techniques, 4×4 block decomposition and efficiently vertical scheduling, are proposed to reuse data among the variable block size and to improve the hardware utilization. Besides, advanced architectures are designed to efficiently integrate the 6-taps 2D finite impulse response, residue generation, and 4×4 Hadamard transform into a fully pipelined architecture. This design is finally implemented and integrated into an H.264/AVC single chip encoder that supports realtime encoding of 720×480 30fps video with four reference frames at 81 MHz operation frequency with 405 K logic gates (41.9% area of the encoder).

A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC

This paper proposes a novel cost-effective and programmable architecture of CAVLC decoder for H.264/AVC, including decoders for Coeff_token, T1_sign, Level, Total_zeros and Run_before. To simplify the hardware architecture and provide programmability, we propose four new techniques: a new group-based VLD with efficient memory (NG–VLDEM) for Coeff_token decoder, a novel combined architecture (NCA) for level decoder, a new group-based VLD with memory access once (GMAO) for Total_zeros decoder and a new VLD architecture based on multiplexers instead of searching memory (MISM) for Run_before decoder. With the above four techniques, the proposed CAVLC decoder can decode every syntax element within one clock cycle. Synthesis result shows that the hardware cost is 3,310 gates with 0.18 μm CMOS technology at a clock constrain of 125 MHz. Therefore, the proposed design is satisfied for real-time applications, such as H.264/AVC HD1080i video decoding.

二维离散5/3小波变换并行VLSI结构设计

提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。     

求图的约束最小割集的一个有效算法及其应用

本文提出确定把无向连通图G(V,E)切割为两个子图G_1(V_1,E_1)和G_2(V_2,E_2)且满足顶点集V_1和V_2的顶点数|V_1|和|V_2|为给定值的约束最小割集的一种有效算法。该算法理论比较简单,步骤简捷有效,并能保证在多项式时间内获得最优解;此外,本文举例说明该算法具体步骤过程并介绍该算法在计算机辅助电路分析和设计中的某些实际应用。     

二维9／7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9／7小波变换（DWT）Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点。这种并行处理的Mesh结构可提高小渡变换电路速度,以及图像压缩的速度。     

ANALYSIS OF A RAIN COMPENSATION ALGORITHM FOR K/Ka-BAND COMMUNICATIONS

A rain compensation algorithm (RCA) has been developed for use in the advanced communications technology satellite (ACTS) mobile terminal (AMT) system. The basic goal of the RCA is to control the transmitted data rates (9·6, 4·8 or 2·4 kbps) in the forward and return links so that a 3 dB link margin is maintained at the highest possible transmitted data rate. In this paper, analyses of both theoretical and practical issues relating to the RCA are presented. In addition, sample simulations of a one-dimensional version of the RCA at the MT are presented which illustrate typical RCA performance using both simulated and recorded pilot fade field data. It is found that with suitable post-processing, the RCA can provide reasonable (conservative) data rate estimates without making excessive data rate changes, i.e., data rate change fluctuations. It is anticipated that the results presented here will not only be useful for the eventual operation of the RCA, but more generally will be useful in the design and operation of other rain compensation techniques for K/Ka-band communication systems.