高分辨率航测CCD图像的无损压缩算法

针对超高分辨率CCD相机拍摄图像,提出了一种无损压缩算法.算法以嵌入式小波零树编码为基础, 通过对零树编码输出的比特平面采用变长游程编码方法很好地提高了图像压缩比.同时,算法将游程编码与比特平面编码统一进行,编码效率大大提高.实验结果表明,该算法的像素平均比特率相对经典的嵌入式小波零树算法均有明显降低.     

基于背景位平面向低位位移的ROI压缩算法研究

针对JPEG2000中一般位移法消耗大量的比特数编码形状信息和最大位移法不能控制感兴趣区域(ROI)与背景(BG)区域相对质量的问题,以及经典多级树集合分裂(SPIHT)压缩算法中忽略小波子带兄弟间相关性的缺点,提出了一种应用于ROI压缩编码的BG位平面向低位位移的移位方法,并对SPIHT压缩编码算法的零树结构进行了改进,在解码端即使BG部分未被反向平移,仍能有较好的结果。通过缩小BG幅值及改进零树结构的SPIHT压缩算法的仿真实验表明,该方法实用有效,适用于较大压缩比及低码率传输的情况。     

一种基于MQ编码器的图像联合压缩加密算法

为实现图像的压缩和加密同步,使用MQ编码器对内嵌零树小波压缩算法进行改进,将混合混沌序列作为流密钥对比特平面编码生成的上下文和判决进行修正,并送入MQ编码器进行熵编码。对算法进行仿真,结果表明:与原压缩算法相比,所提出算法的重构图像PSNR值至少提高了1 dB,且抗攻击性好,加解密速度快。算法实现了分辨率选择性加密,并在数据压缩的同时实现了算术加密。     

一种基于小波系数重要图编码的图像压缩算法

提出了一种新的基于小波系数重要图编码的图像压缩算法。该算法根据量化后的波系数的特点进行了一种期望排序，然后舍掉序列后面大量的零值小波系数，从而得到一个波系数子集，能以少的小波系数来很好地逼近原始图像，省去了零树编码中零树结构带来的大量比特开销。实验表明，该算法与MPEG-4的静止图像压缩算法相比较，重构图像的峰值信噪比（PSNR）值在相同码率下有较大的提高。     

易于硬件实现的内嵌图像编码算法

EZBC算法综合利用了子带内和子带间系数的相关性．把零树／零块结构和基于上下文编码的优点有机结合在一起,获得了比SPHIT算法更好的压缩性能,比EBCOT更高的压缩效率。但是EZBC算法编码中的两个排序链表需要很大且非固定的存储空间,这使得EZBC算法的硬件实现非常困难。在EZBC算法的基础上提出了一种易于硬件实现、低存储量、高压缩性能的内嵌零块图像编码算法。该算法利用比特平面节点重要性状态表和上下文查找表来完成整个编码过程和形成上下文。实验结果表明,所提出的算法具有与EZBC算法基本相同的高压缩性能,但所需存储空间约为EZBC算法的四分之一,所以该算法更易于硬件实现。     

基于空间组合矢量分类的小波图像网格编码矢量量化

本文基于零树编码、矢量分类和网格编码量化的思想,提出了对小波图像采用空间矢量组合和分类后进行网格编码矢量量化的新方法.该方法充分利用了各高频子带系数频率相关性和空间约束性,依据组合矢量能量和零树矢量综合判定进行分类,整幅图像只需单一量化码书,分类信息占用比特数少.对重要类矢量实行加权网格编码矢量量化,利用卷积编码扩展信号空间以增大量化信号间的欧氏距离,用维特比算法搜索最优量化序列,比使用矢量量化提高了0.6db左右.该方法编码计算复杂度适中,解码简单,可达到很好的压缩效果.     

鲁棒的基于等级树分集算法的图像压缩

提出一种基于SPIHT算法编码结构的小波树图像的概念,从图像小波变换系数图中提取出各小波树,然后对各小波树、各比特平面层的编码数据独立打包,按重要性依次发送,来提高整个码流的鲁棒性。实验表明,本算法是相当有效的,即使在很高的丢包率情况下,仍能提供较好的解码图像并保留了它的渐进显示特性。     

一种具有抗误码性能的树块压缩算法

星载图像编码系统要求图像压缩算法具有一定压缩比、低复杂度的特点,同时希望尽可能减少码流比特错误造成的误码扩散。为了减少误码扩散,提出了一种易于硬件实现、低复杂度、抗误码强的树块数据无损压缩算法。图像数据经过小波变换后,将各级分辨率的系数按照树的结构进行排序,并由若干棵相邻的树构成树集合,称之为树块,每个树块独立进行比特平面编码,产生的码流独立进行打包。结果表明,这种编码方法有较低复杂度,易于硬件实现,能够有效优化,使输出码率达到最短,而且可以有效提高系统的抗误码性能。     

一种改进的图像自适应零树编码方法

在研究Shapiro零树图像编码方案的基础上,提出了一种改进型的自适应嵌入式零树编码方法.本算法利用自适应的小波系数,增加了编码过程中零树个数,提高了编码效率,使在相同压缩率情况下,提高PSNR约为0.1~0.6dB,同时该编码方案仍保持零树编码产生嵌入式码流、支持多码率解码的特点.     

一种基于小波变换的遥测图像编码新方法

为了实现火箭遥测图像的高效处理,优化火箭遥测图像的编码流程,提出了一种基于小波变换的火箭遥测图像编码新方法。在图像小波变换的基础上,以空间方向树为编码单位,采用改进的分层树集合分割(SPIHT)算法实现图像重要小波系数的比特平面编码,并采用联合码率优化截取方法,优先截取和传输重要比特平面的遥测图像数据。通过系统测试,结果表明：与传统的火箭遥测图像编码方法相比,新的遥测图像编码方法具有丢帧率低、重构图像质量好、编码效率高等优点,满足运载火箭遥测图像处理和传输的工程需求。     

Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC

Context-based adaptive variable-length coding (CAVLC) is a new and important feature of the latest video coding standard, H.264/AVC. The direct VLSI implementation of CAVLC modified from the conventional run-length coding architecture will lead to low throughput and utilization. In this brief, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4$times$4 blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bitstream. Our dual-block-pipelined architecture doubles the throughput and utilization of CAVLC at high bit rates. Moreover, a zero skipping technique is adopted to reduce up to 90% of cycles at low bit rates. Last but not least, Exp-Golomb coding for other general symbols and bitstream encapsulation for the network abstraction layer are integrated with CAVLC as a complete H.264/AVC baseline profile entropy coder. Simulation shows that our design is capable of real-time processing for 1920$times$1088 30-fps videos with 23.6 K logic gates at 100 MHz.     

基于JPEG2000的高速MQ算术编码器的研究与实现

提出了一种基于流水线技术的高速MQ算术编码器的VLSI实现架构。文中采用表扩展及乒乓buffer输出,同时对标准编码流程进行了优化及调整,以适合VLSI高速实现。结构采用流水线技术,将整体架构分为三个流水级,极大的提高了处理速度。经Xilinx公司的FPGA验证,本结构的处理速度可达到1bit/cycle(47.292Mbit/sec)。     

A HIGH-PERFORMANCE VLSI ARCHITECTURE OF EBCOT BLOCK CODING IN JPEG2000

The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.     

VLSI architecture of bit-serial quasicyclic encoders

A bit-serial algorithm for the multiplication of elements in the vector space of finite dimension is presented. Based on the algorithm, a VLSI architecture of quasicyclic (QC) encoders is shown. Compared with that of conventional QC encoders, the proposed architecture is more regular, simpler and programmable. It also offers designers more flexibility for choosing available VLSI techniques. In addition, it can easily be changed to accommodate any QC coding strategies.     

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 m CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base.     

基于JPEG2000的遥感图像感兴趣区域编码新算法及其VLSI设计

为解决空间遥感图像数据量及信道带宽之间的矛盾,该文提出一种基于JPEG2000的感兴趣区域(Region Of Interest, ROI)编码算法。主流的JPEG2000 ROI编码算法难以兼顾ROI质量和系统计算量,且在低码率编码时有完全丢失背景的隐患。该算法通过精确控制各子带中背景系数的精度,使ROI分配到更多码流。并引入了人眼视觉特性,使较少的背景码流产生尽量好的视觉效果。另外,根据该算法提出了针对矩形ROI的超大规模集成电路(VLSI)设计,此设计经过简单调整,亦可适用于主流的ROI编码算法。测试结果表明,该算法在ROI质量和重建图像视觉效果上均表现优异,且支持任意形状ROI编码,兼容JPEG2000协议。该VLSI设计仅使JPEG2000系统运行时间增加一个周期,具有极高的吞吐率,可满足实时处理要求。     

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.     

Highly scalable wavelet-based video codec for very low bit-rateenvironment

We introduce a highly scalable video compression system for very low bit-rate videoconferencing and telephony applications around 10-30 kbits/s. The video codec first performs a motion-compensated three-dimensional (3-D) wavelet (packet) decomposition of a group of video frames, and then encodes the important wavelet coefficients using a new data structure called tri-zerotrees (TRI-ZTR). Together, the proposed video coding framework forms an extension of the original zero tree idea of Shapiro (1992) for still image compression. In addition, we also incorporate a high degree of video scalability into the codec by combining the layered/progressive coding strategy with the concept of embedded resolution block coding. With scalable algorithms, only one original compressed video bit stream is generated. Different subsets of the bit stream can then be selected at the decoder to support a multitude of display specifications such as bit rate, quality level, spatial resolution, frame rate, decoding hardware complexity, and end-to-end coding delay. The proposed video codec also allows precise bit rate control at both the encoder and decoder, and this can be achieved independently of the other video scaling parameters. Such a scheme is very useful for both constant and variable bit rate transmission over mobile communication channels, as well as video distribution over heterogeneous multicast networks. Finally, our simulations demonstrated comparable objective and subjective performance when compared to the ITU-T H.263 video coding standard, while providing both multirate and multiresolution video scalability     

Algorithm analysis and architecture design for rate distortion optimized mode decision in high definition AVS video encoder

There are abundant intra and inter prediction modes in the AVS video coding standard. Rate distortion optimized mode decision can fully utilize this flexibility to improve the spatio-temporal prediction efficiency and maximize the coding efficiency. However, the implementation complexity is dramatically high due to huge throughput burden. Hardware oriented mode decision algorithm is tailored for VLSI implementation in this work for high definition video coding. Mode preselection is employed to alleviate the dramatic throughout burden. Also, intelligent pipeline scheduling mechanism is proposed to break the intrinsic data dependency in intra prediction, which is directly related with mode decision. The proposed simplified algorithm is well-suited for hardware implementation with small performance penalty. Finally, the VLSI architecture is proposed with good trade off between circuit consumption and rate distortion performance.     

一种低功率分层运动估值器的VLSI结构设计

本文提出一种新的低功率分层运动估值器的VLSI结构,它支持低比特视频编码器的高级预测模式,如H.263和MPEG-4。为减少芯片尺寸及功率消耗,在所有搜索层中使用同一个基本的搜索单元 (BSU)。另外,通过对数据流的有效控制,使其在高级预测模式下,在获得宏块运动矢量的同时,也获得每个宏块中的4个88子块的运动矢量。实验结果表明,这种结构采用较少的门电路,有效降低了功率消耗,并且实现了与全搜索块匹配算法(FSBMA)相似的编码效果,可广泛应用于无线视频通信所需的低功率视频编码器中。