Temperature dependence of field-controlled thyristor characteristics

The dependence of the characteristics of field-controlled thyristors upon the ambient temperature has been examined in the range of -30 to 200°C. Unlike conventional thyristors, these devices have been found to continue to exhibit forward blocking capability up to the highest measurement temperature (200°C). In fact, it is shown here that the forward blocking capability as well as the blocking gain improve with increasing temperature with the usual scaling of the leakage current for power devices. The reverse blocking capability is also retained. The forward voltage drop of the device in the conducting state decreases with increasing temperature. This behavior is shown to be similar to that of conventional rectifiers and thyristors operated at high injection levels. Further, the force gate turn-off time of the devices has been found to increase with increasing temperature. This has been correlated with a measured increase in the minority-carrier lifetime. The results of this study demonstrate that field-controlled thyristors are capable of being operated at higher temperatures than conventional thyristors.     

High-voltage junction-gate field-effect transistor with recessed gates

A new recessed-gate structure for vertical-channel junction field-effect transistors (JFET's) is described together with a self-aligned gate-source process developed to fabricate these devices. Using this technology, devices with groove depths ranging from 8 to 18 µm have been fabricated. The characteristics of these devices is described as a function of the groove depth. It has been found that the devices display pentode-like characteristics at low gate voltages and triode-like characteristics at high gate voltages. The blocking gain has been found to increase with groove depth. However, this is accompanied by an increase in the on-resistance and a decrease in the saturated drain current. Devices with gate breakdown voltages of up to 600 V have been fabricated with the recessed-gate structure. These high-voltage field-effect transistors (FET's) have a unity power gain cutoff frequency of 600 MHz and gate turn-off times of less than 25 ns.     

A power junction gate field-effect transistor structure with high blocking gain

A new gate structure is described for vertical-channel power junction gate field-effect transistors (FET's). This gate structure has vertically walled gate regions extending perpendicular to the wafer surface. The structure is fabricated by using orientation-dependent silicon etching and selective vapor-phase epitaxial refill techniques. In comparison to previous gate structures made by planar diffusion, the vertically walled gate structure exhibits one order of magnitude improvement in blocking gain. This improvement in blocking gain has allowed the fabrication of devices having breakdown voltages above 400 V and a current-handling capability of more than 0.5 A with an on-resistance of 12 Ω. The devices are designed to exhibit pentode-like characteristics at low gate voltages and triode-like characteristics at large reverse gate bias voltages in order to obtain the observed high-power handling capability.     

1.1 kV 4H-SiC power UMOSFETs

Silicon Carbide (4H-SiC), power UMOSFETs were fabricated and characterized from room temperature to 200°C. The devices had a 12-μm thick lightly doped n-type drift layer, and a nominal channel length of 4 μm. When tested under Fluorinert^TM at room temperature, blocking voltages ranged from 1.0 kV to 1.2 kV. Effective channel mobility ranged from 1.5 cm²/V.s at room temperature with a gate bias of 32 V (3.5 MV/cm) up to 7 cm²/V.s at 100°C with an applied gate bias of 26 V (2.9 MV/cm). Specific on-resistance (R_on,sp) was calculated to be as low as 74 mΩ.cm² at 100°C under the same gate bias     

A high-voltage optoelectronic GaAs static induction transistor

Experimental realization of an optically activated, high-voltage GaAs static induction transistor (SIT) is reported. In the forward blocking state, the breakdown voltage of the device was ~200 V, while in the conduction state, on-state current densities exceeding 150 A/cm² were obtained. In the floating-gate configurations (gate open), the specific on-resistance of the device was ~50 mΩ-cm². Optical modulation of the device was achieved using a compact semiconductor laser array as the triggering source. In this mode, a gate-coupled RC network was implemented, resulting in an average switching energy gain (load energy/optical energy) of ~30. This mode of operation is applicable to series-coupled devices for pulsed switching at higher power levels     

1200 V常开型4H-SiC VJFET

用沟槽和离子注入方法在自主外延的4H导通型碳化硅晶圆上研制了垂直沟道结型场效应晶体管(VJFET).在栅电压V<,G>=-10 V时阻断电压达到1 200 V;在V<,G>=2.5 V,V<,D>=2V时的电流密度为395 A/cm<'2>,相应的比导通电阻为5.06 mΩ·cm<'2>.分析发现欧姆接触电阻是导通电阻...     

High-performance vertical-power DMOSFETs with selectively silicidedgate and source regions

A power FET (field-effect transistor) structure with selectively silicided gate and source region is described. This structure simultaneously lowers the gate sheet-resistance and the source contact resistance. The gate-source isolation was provided by plasma etching conformally deposited chemical vapor deposition (CVD) oxide using a photoresist mask. This structure has resulted in an order of magnitude improvement in the gate sheet resistance and about 25% improvements in the device's on-resistance (the resistance when conducting in the on-state) compared to previously reported nonsilicided conventional power FETs. Extremely low-resistance Al-TiW-TiSi₂ metallurgy with in situ sputter etching of the silicide surface prior to TiW deposition contributed to the reduction in the on-state resistance. Vertical-power DMOSFETs (double-diffused MOSFET) fabricated using this technology have a specific on-resistance of 0.53 Ω cm² for devices capable of blocking 50 V in the off state     

High-voltage bipolar mode JFET with normally off characteristics

The first realization of a power vertical JFET operated in the bipolar mode (BJFET) with normally off behavior is reported. The structure combines minority carrier injection from the gate region in the on-state, and lateral pinch-off of the channel, due to the built-in voltage, in the off-state. The realized devices show high blocking voltages, up to 900 V, with zero gate bias, and have extremely low on-resistance. Fast switching speeds with forced gate turn-off times as low as 100 ns for devices of 600-V blocking voltages have been obtained.     

35-GHz performance of single and quadruple power heterojunction HEMT's

The potential of single hetrojunction (SHJ) and quadruple heterojunction (QHJ) HEMT devices to provide power amplification at theKa-band frequencies has been measured. The power level observed, from QHJ devices that have gate lengths of 0.5 µm and gate widths of 200 µm, has been over +20 dBm when gain is compressed below the small signal level by 2 dB. The small-signal gain was 5.2 dB at 35 GHz. The power level demonstrated by the SHJ devices is lower than that of the QHJ devices due to the lower "two-dimensional electron gas" sheet carrier density. Our measurements have shown a saturated power level of +15.3 dBm devices of the same geometry as the above-mentioned QHJ devices. The power performance in both cases (QHJ and SHJ) has been obtained with high efficiencies of 38 and 21 percent, respectively. These performance data represent the highest levels of gain and power reported atKa-band frequencies from transistors that employ a 0.5-µm geometry.     

High-power conductivity-modulated FET's (COMFET's) with a p-type channel

In previous work, a conductivity-modulated field-effect transistor (COMFET) having drastically reduced on-resistance was described; that device was based on n-channel MOS technology. In this letter, we report the development of a complementary device-the p-channel COMFET. These new p-channel COMFET's have demonstrated dc on-resistance values as low as 0.07 Ω at 20 A (for a 3 mm × 3 mm pellet), while providing forward blocking voltages of 200-400 V. To our knowledge, this on-resistance value (normalized to the same active area) is lower than that of any p-channel power MOSFET (even those with blocking voltages of only 100 V) and as much as 30 times less than that of a p-channel MOSFET with a comparable blocking-voltage capability. Using suitable minority-carrier-lifetime control techniques, drain-current-decay times have been reduced from ≈ 30 µs to below 1 µs.     

1200 V 4H-SiC Bipolar Junction Transistors with A Record β of 70

A common current gain of 70 has been achieved in 4H-SiC bipolar junction transistors (BJTs) at room temperature, which is the highest among those reported. BJTs having an active area of 4 mm × 4 mm exhibit a specific on-resistance of 6.3 mΩ cm² at 25°C, which increases to 17.4 mΩ cm² at 250°C. BV_CEO (the breakdown voltage from collector to emitter with open base) and BV_CBO (the breakdown voltage from collector to base with open emitter) of 1200 V were observed at <5 μA leakage currents at all temperatures up to 250°C. Dynamic characteristics were measured using the IXYS RF/Directed Energy IXDD415 gate driver evaluation board to drive the BJT. A collector current (I _C) rise time at turn-on of 32 ns was measured with a 1.6 A gate current provided to support the collector current of 63 A. An I _C fall time at turn-off of 16 ns was achieved.     

800 V 4H-SiC RESURF-type lateral JFETs

This letter proposes to show that a lateral switching device has some unique advantages, including little dependence on substrate defects, low on-resistance, and a simple design of heat radiation. A reduced surface field (RESURF) type SiC-JFET is one of candidate devices for an electric or hybrid automobile application. Small RESURF-type SiC-JFETs with gate width of 200 /spl mu/m and a blocking voltage of 800 V were fabricated. The fabrication and characteristics of the devices are described and discussed.     

Power absorption capability of punch-through devices

The power absorption capability and high-current characteristics of silicon high-voltage punch-through structures were investigated. Impact ionization was observed in the devices using 100- and 75-ohmċcm base material. The transient power absorption capability of these structures was found to be less temperature-dependent than that of avalanche devices. With proper surface contouring, a power absorption capability of 48 kW/cm²at 10 µs was achieved at a junction temperature of 26°C and 38 kW at 200°C for devices made of 350-ohmċcm base material.     

Electron irradiation of field-controlled thyristors

The influence of 3-MeV electron irradiation upon the characteristics of asymmetrical field-controlled thyristors has been examined for fluences of up to 16 Mrad. In addition to the lifetime reduction due to the radiation damage, carrier removal effects have also been observed in the very lightly doped n-base region of these devices. The leakage current, even after radiation at the highest fluenee, is not significantly increased and the blocking characteristies of these devices are not degraded. In fact, a small improvement in the blocking gain has been observed at low gate voltages. The electron irradiation has been found to increase the forward voltage drop during current conduction and to reduce the forced gate turn-off time. Gate turn-off times of less than 500 ns have been achieved by irradiation with a fluence of 16 Mrad. However, this is accompanied by a large increase in the forward voltage drop. Tradeoff curves between the forward voltage drop and the gate turn-off time have been obtained. From these curves, it has been determined that gate turnoff times of 1 µs can be obtained without a significant increase in the forward voltage drop for devices capable of blocking up to 600 V.     

Temperature behavior and annealing of insulated gate transistors subjected to localized lifetime control by proton implantation

Localized lifetime control by proton implantation can result in a considerable improvement in the trade-off between device turn-off time and forward voltage when compared with the unlocalized method of electron irradiation. After a proton dose of 3 × 10¹¹cm⁻² at 3.1 MeV implanted here into insulated gate transistors, turn-off time is reduced by more than an order of magnitude compared to unimplanted devices. When the implanted devices are operated as high voltage switches at a current of 152 A cm⁻² and at a forward blocking voltage of 400 V, the following increases are observed by increasing device operating temperatures from 20 to 150°C, (a) forward voltage: 2.5 V to 2.7 V; (b) turn-off time: 0.78 μs to 1.23 μs; (c) leakage current: 20 nA to 1 mA. The physical mechanisms responsible for the qualitative temperature dependences are identified: MOS channel resistance for forward voltage, carrier capture cross-section for turn-off time, and generation and diffusion components of leakage current. Since no catastrophic or unrecoverable behavior is observed, normal device operation within the tested temperature range is possible. Isothermal annealing curves of turn-off time measured after annealing, and corresponding to a few hours annealing time, reveal that a constant turn-off time is reached after about an hour. The constant value increases with temperature, but is still below the unimplanted value after 4 h at 525°C. The turn-off time was verified to be constant even after 24 h of annealing at 200°C. Lifetime control by proton implantation seems to be more thermally stable than that caused by electon irradiation.     

Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.     

The planar 6H-SiC ACCUFET: a new high-voltage power MOSFETstructure

A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P⁺ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 mΩ.cm² at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10¹⁶ cm^-3, 10 μm), which is capable of supporting 1500 V     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

High-efficiency 35-GHz GaAs MESFET's

Ka-band GaAs FET's with power output in excess of 200 mW and with efficiencies of more than 20 percent are described. Both ion-implanted and VPE-grown wafers were used. Deep UV (300-nm) lithography and chemical etching was employed to obtain a final gate length of 0.5 µm. These FET chips were flip-chip mounted and had a very low thermal resistance of 50°C/W for a total source periphery of 0.6 mm. At 35 GHz an output power of 220 mW with 21-percent efficiency at 3-dB gain was obtained from a 0.6-mm cell.     

The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.