Dry etching technology for 1-µm VLSI fabrication

A dry etching technology for 1-µm VLSI has been developed. This technology led to successful fabrication of a 1-µm 256-kbit MOS RAM using electon-beam direct writing and molybdenum-polysilicon double-gate structure. Silicon nitride, silicon dioxide, phosphosilicate glass, polysilicon, single-crystal silicon, molybdenum, and aluminum are etched by parallel-plate RF diode reactors. Resist patterns are used as etching masks. The negative resist is CMS and the positive resist is FPM. Plasma polymerization is found to have significant effect on etching selectivity, undercutting, and residue. Directional etching profiles are realized and 1-µm patterns with less than 0.05-µm undercutting are obtained. High etching selectivities are achieved. Methods for preventing and removing contamination as well as damage are established. With these, dry etching proves to bring no adverse effects on device characteristics. Pattern-width fluctuations caused by negative-resist pattern foot are decreased to below 0.1 µm by a new foot trimming technique. Resist step coverage is also clarified.     

A fine emitter transistor fabricated by electron-beam lithography for high-speed bipolar LSI's

A highly stable, high-performance bipolar transistor with a 1/4-µm emitter is developed. This is accomplished by using advanced electron-beam (EB) lithography and polysilicon reactive ion etching (RIE). Results show that the minimum emitter width is only 0.2 µm and the emitter width accuracy is ±0.06 µm. In addition, the gate delay is reduced from 190 to 100 ps/gate for 25-stage, three-input ECL circuits. The effects of an ultra-narrow emitter on transistor characteristics are also studied.     

Laser ultrasonic study of porous silicon layers

Propagation of ultrasonic signals induced by nanosecond laser pulses in porous silicon (por-Si) is considered from both the theoretical and the experimental viewpoints. The experimental samples are por-Si layers with 5-to 40-µm thickness and porosity of 50–75%; these layers were formed on a single-crystal silicon substrate by electrochemical etching. It is shown that the suggested ultrasonic laser method allows both the thickness and the porosity of a layer to be determined with the respective accuracies of no worse than 1 µm and 5%.     

Low-loss fiber-matched low-temperature PECVD waveguides with small-core dimensions for optical communication systems

Plasma-enhanced chemical vapor deposition (PECVD) offers a simple way of fabricating (doped) silica layers on silicon. A new design of the waveguide core allows low-loss fiber matched waveguides with low birefringence without high-temperature annealing. The increased loss of doped plasma deposited silica due to hydrogen incorporation is overcome by reducing the core dimensions and increasing the refractive index contrast. The waveguides can easily be fabricated using standard PECVD technologies and resist masked reactive ion etching (RIE) etching. Integrated optical devices such as 1/spl times/8 power splitters, 1300/1550-nm wavelength multiplexers and thermooptical switches were successfully fabricated and tested.     

A 2-µm silicon-gate C-MOS/SOS technology

A 2-µm silicon gate deep-depletion C-MOS/SOS technology is described and characterized. The fabrication technology features all dry processing (ion milling and plasma etching) ion implanted source and drain, 2-µm features on all levels, phosphorous glass reflow for improved yield, and low-temperature processing (T ≤ 875°C). Characterization of the static electrical parameters as a function of channel length is presented. Circuit performance was characterized using a ring oscillator and a pattern generator. The ring oscillator exhibited stage delay as small as 220 ps at 5 V and an associated speed power product of less than 5 pJ. The pattern generator achieved an 80-MHz data rate. The potential of this technology for extension to submicrometer geometries was demonstrated by fabrication of discrete transistors with O.5-µm channel lengths.     

Plasma etching of polysilicon and Si3N4in SF6with some impact on MOS device characteristics

Accurate delineation of the circuit materials polycrystalline silicon ("poly"), and silicon nitride are important requirements of most SFC process sequences. We have investigated the use of SF6as an active species in the parallel-plate plasma etching of these materials. For the etching of poly there is good selectivity (better the 50:1) with respect to the etch rates of SiO2and positive photoresist. This process has been used in the fabrication of MOS transistor with 3-µm poly-gate lengths and threshold voltages vary by less than 0.05 V both across a wafer and from wafer to wafer. Etching of nitride is less selective and less isotropic than that of poly.     

1-µm MOS process using anisotropic dry etching

Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CCl3F gas. The Si to SiO2etch-rate ratio was 5 : 1. This etch process in CCl3F was interpreted as mainly involving physical reaction as opposed to etching in SF6. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wetetch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si3N4, polysilicon, SiO2, and aluminum, was applied to the fabrication of a 1-kbit static RAM with 1-µm minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-µm MOSLSI manufacturing process.     

Highly reliable high-voltage transistors by use of the SIPOS process

The n-p-n and p-n-p high-voltage transistors showing high reliabilities have been developed by using semi-insulating polycrystalline-silicon (SIPOS) films for the surface passivation. SIPOS films are chemically vapor-deposited polycrystalline-silicon doped with oxygen or nitrogen atoms. The films employed for the surface passivation of high-voltage transistors are composed of triple layers, which are oxygen-doped SIPOS films of 0.5-µm thickness to stabilize the silicon interface, nitrogen-doped SIPOS films of 0.15-µm thickness to prevent water or sodium ions from reaching the silicon surface, and silicon dioxide films to prevent dielectric breakdown of the SIPOS films under very high-voltage operation. The n-p-n and p-n-p SIPOS transistors rated at 800 and 2500 V have been produced in planar-like structures with field-limiting rings. These transistors showed highly reliable characteristics, because the passivating SIPOS layer provides a good protection against ionic contamination and externally applied electric fields. Furthermore, 10-kV n-p-n SIPOS transistors with multiple rings have been fabricated and found that operation is stable.     

Boron ion implantation in silicon through selectively deposited tungsten films

The effect of implanting boron into silicon through thin selective tungsten films and annealing to form silicided p⁺-n junctions is investigated. A rate limited thickness of 0.011-µm tungsten is shown to have the equivalent stopping power of 0.08-µm oxide and be similarly ineffective in eliminating axial boron channeling. Nonetheless, junction diodes as shallow as 0.25µm with sheet resistances of 7 Ω, exhibiting nearly idealI-Vcharacteristics from -40 to 100°C, are fabricated. Analysis of the areal and perimeter leakage currents suggests that defects at the WSi2-SiO2interface are the contributing generation-recombination sites.     

SiCl4-based reactive ion etching of ZnO and MgxZn1−xO films on r-sapphire substrates

SiCl₄-based reactive ion etching (RIE) is used to etch Mg_xZn_1−xO (0≤x≤0.3) films grown on r-plane sapphire substrates. The RIE etch rates are investigated as a function of Mg composition, RIE power, and chamber pressure. SiO₂ is used as the etching mask to achieve a good etching profile. In comparison with wet chemical etching, the in-plane etching anisotropy of Mg_xZn_1−xO (0≤x≤0.3) films is reduced in RIE. X-ray photoelectron spectroscopy measurements show that there is no Si and Cl contamination detected at the etched surface under the current RIE conditions. The influence of the RIE to the optical properties has been investigated.     

One-dimensional photonic crystal obtained by vertical anisotropic etching of silicon

The potentialities of vertical anisotropic etching of (110) silicon for the fabrication of one-dimensional photonic crystal with a high refractive index contrast have been studied. It is shown that advances toward the near-IR spectral range are limited by the mechanical strength of thin silicon walls. The device structures obtained consist of 50 trenches, 114 μm deep, with 1.8-μm-thick Si walls (structure period 8 μm). Their reflectance spectra in the wavelength range 2.5–16.5 μm show good agreement with calculation results, although the main photonic band gap at λ≈28±10 μm remained outside the spectral region of measurements. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 36, No. 8, 2002, pp. 996–1000. Original Russian Text Copyright ? 2002 by Tolmachev, Granitsyna, Vlasova, Volchek, Nashchekin, Remenyuk, Astrova.     

Characteristics of large‐scale nanohole arrays for thin‐silicon photovoltaics

Nanostructured crystalline silicon is promising for thin‐silicon photovoltaic devices because of reduced material usage and wafer quality constraint. This paper presents the optical and photovoltaic characteristics of silicon nanohole (SiNH) arrays fabricated using polystyrene nanosphere lithography and reactive‐ion etching (RIE) techniques for large‐area processes. A post‐RIE damage removal etching is subsequently introduced to mitigate the surface recombination issues and also suppress the surface reflection due to modifications in the nanohole sidewall profile, resulting in a 19% increase in the power conversion efficiency. We show that the damage removal etching treatment can effectively recover the carrier lifetime and dark current–voltage characteristics of SiNH solar cells to resemble the planar counterpart without RIE damages. Furthermore, the reflectance spectra exhibit broadband and omnidirectional anti‐reflective properties, where an AM1.5 G spectrum‐weighted reflectance achieves 4.7% for SiNH arrays. Finally, a three‐dimensional optical modeling has also been established to investigate the dimension and wafer thickness dependence of light absorption. We conclude that the SiNH arrays reveal great potential for efficient light harvesting in thin‐silicon photovoltaics with a 95% material reduction compared to a typical cell thickness of 200 µm. Copyright © 2012 John Wiley & Sons, Ltd.     

Deep UV 1:1 projection lithography utilizing negative resist MRS

A negative deep UV resist Micro Resist for Shorter wavelengths (MRS) is successfully applied to 1:1 projection printing. The MRS is characterized by strong absorption of deep UV light and absence of swelling in the developer. It resolves steep profile images of 1-µm linewidth in 1-µm-thick films. The resist has extremely high sensitivity to deep UV light. Scanning exposure time necessary for a 4-in wafer is about 25 s. The MRS exhibits dry etching resistance superior to that of an AZ-type positive resist. Furthermore, MRS is not adversely affected by reflected light from stepped aluminum surfaces. Application of MRS should open the way to realization of a practical deep UV 1:1 projection lithography featuring high resolution and throughput.     

Variable-shaped electron-beam direct writing technology for 1-µm VLSI fabrication

A 1-µm 256K MOS RAM has been fabricated using a variable-shaped electron-beam (EB) direct writing technology. EB drawing data are prepared using a new program, PEBL, which includes a new algorithm for shot division. PEBL plays an important role in obtaining high EB system throughput and high quality patterns. A new proximity correction technique, DCA, has also been proposed. This technique is simple and very effective in fabricating 1-µm VLSI patterns. Negative resist CMS or positive resist FPM are used appropriately, according to process levels. In fabrication of a 1-µm 256K MOS RAM, ±0.2-µm overlay accuracy and ±0.1-µm linewidth accuracy were achieved.     

Controlled Microfabrication of High‐Aspect‐Ratio Structures in Silicon at the Highest Etching Rates: The Role of H2O2 in the Anodic Dissolution of Silicon in Acidic Electrolytes

In this work the authors report on the controlled electrochemical etching of high‐aspect‐ratio (from 5 to 100) structures in silicon at the highest etching rates (from 3 to 10 µm min^?1) at room temperature. This allows silicon microfabrication entering a previously unattainable region where etching of high‐aspect‐ratio structures (beyond 10) at high etching rate (over 3 µm min^?1) was prohibited for both commercial and research technologies. Addition of an oxidant, namely H₂O₂, to a standard aqueous hydrofluoric (HF) acid electrolyte is used to dramatically change the stoichiometry of the silicon dissolution process under anodic biasing without loss of etching control accuracy at the higher depths (up to 200 µm). The authors show that the presence of H₂O₂ reduces the valence of the dissolution process to 1, thus rendering the electrochemical etching more effective, and catalyzes the etching rate by opening a more efficient path for silicon dissolution with respect to the well‐known Gerischer mechanism, thus increasing the etching speed at both shorter and higher depths.     

HBr反应离子刻蚀硅深槽

对ＨＢｒ反应离子刻蚀硅和ＳｉＯ２进行了实验研究。介绍了ＨＢｒ等离子体的刻蚀特性，讨论了ＨＢｒ反应离子刻蚀硅的刻蚀机理，研究了ＨＢｒ中微量氧、碳对ＨＢｒＲＩＥ刻蚀过程的影响。实验表明，ＨＢｒ是一种刻蚀硅深槽理想的含原子溴反应气体。采用ＨＢｒＲＩＥ，可获得高选择比（对Ｓｉ／ＳｉＯ２）和良好的各向异性。     

Fabrication of monolithically Peltier-cooled linear laser diodes using wet chemical etching

The basic structure of a monolithically Peltier-cooled laser (MPCL) diode has been fabricated. The process of forming the structure involves critical masking and etching processes. A reliable etching process that was capable of producing clean mesas 50 µm wide × 300 µm long and of a height greater than 150-µm was developed using buffered hydrofluoric acid. The mask used-with the buffered hydro-fluorice etchant was Shipley AZ1350B photoresist. This combination of the etchant and the mask process gave good results even when etching a grid pattern consisting of an array of 2-µm-wide lines to form mesas 3.74 µm high. It was found that the etch tends to follow the cleaved planes that intersect the     

A study of far-field patterns from high performance 1.3-µm InGaAsP-InP edge-emitting LED's

Liquid-phase epitaxy InGaAsP-InP 1.3-µm edge-emitting LED's are fabricated with a very simple Schottky-delineated stripe structure. With a stripe 50 µm wide and 200-250 µm long, typical characteristics of these devices include 170 µW of optical power coupled into a 60-µm core 0.2-NA graded index fiber, 600-Å spectral halfwidths, 2-5-ns risetimes. Unlike GaAs-GaAlAs edge-emitting LED's, best results of coupling efficiency are obtained with InGaAsP-InP LED's whose active layer thickness is in the range 0.12-0.15 µm, due to asymmetry in the far-field patterns. Our study of these far-field patterns shows that this asymmetry is governed by the quality of the active layer material located near the InGaAsP-nInP hetero-interface.     

Zone-melting recrystallization of polycrystalline silicon films on fused silica substrates using RF-Heated carbon susceptor

High-quality recrystallized silicon films on fused silica substrates have been produced with a new micro-zone-melting method using an RF-heated carbon susceptor. In this method, the fused silica substrate, on which a 0.5-1.0-µm-thick polycrystalline silicon film encapsulated with a 1.2-µm-thick CVD-SiO2layer has been deposited, is moved across the carbon susceptor surface, which has a narrow-strip high-temperature zone. Recrystallized silicon films with     

H2-based dry plasma etching for mesa structuring of HgCdTe

An experimental study has been carried out on the performance of n-type x = 0.31 HgCdTe photoconductive detectors in order to evaluate two different etching techniques; dry plasma etching, in the form of H₂/CH₄ reactive ion etching (RIE), and wet chemical etching using bromine in hydrobromic acid. Two-dimensional laser beam-induced current (LBIC) imaging was employed as an in-line process monitoring tool to evaluate the lateral extent of reactive ion etching (RIE) induced doping changes in the HgCdTe epilayer following mesa delineation. Responsivity and noise measurements were performed on fabricated mid-wavelength infrared (MWIR) photoconductive devices to evaluate the influence dry plasma etching has on material properties. For a signal wavelength of 3 μm, 60° field of view, and a temperature of 80 K, background limited D _λ ^* performance was recorded for wet chemical processed devices but not for the dry plasma processed devices. The D _λ ^* values obtained for wet chemical and dry plasma etched photoconductive detectors were 2.5×10¹¹ cmHz^1/2W⁻¹ and 1.0×10¹⁰ cmHz^1/2W⁻¹, respectively. Mercury annealing, which has been shown to restore the electrical properties of dry plasma processed HgCdTe, could be used to lessen the influence that RIE dry plasma etching has on photoconductor detector performance.