Josephson-logic devices and circuits

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.     

Optoelectronic component arrays for optical interconnection ofcircuits and subsystems

The design and performance of arrays of hybrid optoelectronic detector and modulator elements for use as optical input and output pads for chip- and board-level optical interconnects are discussed. The application of these interface arrays to specific VLSI circuits is discussed, illustrating the potential improvements in performance levels. This solder bond technique is capable of very accurate component positioning at points across the entire surface of the VLSI circuit, so that precise alignment to the optical pathways can be envisaged with optical signals taken from or delivered to any position on the chip. Measurements presented indicate that submicron positioning can be achieved. In particular, a fabrication-tolerant modulator design incorporating a chirped semiconductor mirror is reported     

A multigigahertz Josephson-semiconductor interface circuit using77-K differential monolithic HEMT amplifier and 4.2-K JJ high-voltagedriver for superconductor-semiconductor electronic hybrid systems

We proposed and successfully demonstrated a high-speed Josephson IC to semiconductor IC output interface circuit combining a high electron mobility transistor (HEMT) amplifier and Josephson high-voltage drivers successfully. We developed a 0.5-μm gate 77-K wide-band analog monolithic HEMT amplifier for the interface. The HEMT device consisted of InGaP/InGaAs materials stable even at 77 K. The amplifier has a differential amplifier as a first stage to cancel out ground-level fluctuations in the Josephson IC and showed a voltage gain of 23 dB and ~3-dB frequency of 8 GHz. A 0.63-V_p-p output was obtained from a 5-GHz, 30-mV_p-p complementary input signal. We succeeded in transfer ring a voltage signal from 10-stack Josephson high-voltage drivers to a 50-Ω system at room temperature with 0.7-V_p-p amplitude at 300-MHz clock using the HEMT amplifier     

Optical interconnects for neural and reconfigurable VLSIarchitectures

The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However, in order to exploit efficiently the potential of thousands of optical off-chip interconnects, an appropriate VLSI architecture is required. We show for the example of neural and reconfigurable VLSI architectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well modulators functioning as two-dimensional (2-D) optical input/output (I/O) interface for the chip is presented. Due to the parallel optical interface, and improvement of two to three orders of magnitude in the throughput performance is possible compared to all-electronic solutions. For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module. Such a system has been fabricated and experimentally characterized. Furthermore, we designed an manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits     

A new peak detector based on usage of second-generation current conveyors

A new precision peak detector (full-wave rectifier) of input sinusoidal signals, which employs four two second-generation current conveyors and five metal-oxide-semiconductor transistors, is presented in this paper. The circuit gives a dc output voltage that is the peak input voltage over a wide frequency range, with a very low ripple voltage and low harmonic distortion. The proposed circuits use an all-pass filter as a 90° phase shifter of the processed input signal. The results of the calculations are verified using SPICE simulations.     

Current polarity switching decoders for Josephson memory arrays

Two new types of Josephson decoder circuits have been devised, designed, fabricated, and tested. The circuits utilize current polarities along address loops as information. This results in simple circuit configurations with about half the number of circuit gates than conventional Josephson decoder circuits. This contributes to improved yield rates and to a decrease in circuit area. One of the two decoder circuitsz described in this paper can be operated with either dc or unipole while the other is unipole only. Using computer simulation, the operating speed for the former 5-32 decoder circuit is about 320 ps which is almost the same as that of conventional decoders, while for the latter circuit it is 115 ps which is almost half of that for the conventional decoders. The decoders are designed with operating margins of over ±35 percent which is sufficient for Josephson circuits. Critical path subsections of these two 5-32 decoder circuits were fabricated by standard lead-alloy technology and quasi-staticaUy operated successfully.     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。     

Design and application of CMOS bulk input scheme

This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V.     

Low power low noise high speed tunable CMOS radiation detection system

This paper presents a design of low power and low noise, high speed readout front-end system for semiconductor detectors. The architecture comprises a folded cascode charge sensitive amplifier with gain enhancement, a pole-zero cancellation circuit and a complex shaper circuit with Gm-C topology. A local feedback amplifier based on a wide swing gain boosting scheme with dc level shifting has been used. The system has been fabricated in a 0.13-µm CMOS technology with a single 1.2-V supply voltage. Experimental results show the flexibility of the system where the key parameters, such as decay time, charge gain and peaking time can be tuned. For a nominal peaking time of 150 ns the power consumption of the entire channel is less than 5 mW. A power consumption-low noise tradeoff will be considered to match a detector capacitance of 5 pF. The output pulse has a peak amplitude of 200 mV for a charge of 10 fC from the detector and achieves a linearity better than 1% up to an input charge range of 12 fC.     

A new tunable current-mode peak detector

The paper presents a completely new realization of peak detector/full-wave rectifier of input sinusoidal signals employing four CCCIIs (controlled current conveyors), metal-oxide–semiconductor transistors and a single grounded capacitor, without any external resistors and components matching the requirements. The circuit gives a DC output voltage that is the peak input voltage over a wide frequency range, with a very low ripple voltage and low harmonic distortion. The proposed circuit uses an all-pass filter as a 90° phase shifter of the square value of the processed input signal. The proposed circuit is very appropriate to be further developed into integrated circuits. To verify the theoretical analysis, the circuit HSPICE simulations were also included, showing good agreement with the theory.     

LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively     

High Gain Equalizing Amplifier Integrated Circuits for a Gigabit Optical Repeater

Equalizing amplifier circuits for a gigabit optical-fiber transmission system are integrated on two monolithic chips implementing an advanced silicon bipolar process. Several new circuit techniques such as a broad-band 50-/spl Omega/ matching amplifier and an electrically controlled and adjusted peaking technique are employed. It is clarified that the main degradation factors of circuit stability are parasitic capacitance between the input and output terminals, and the crosstalk occuring through the wire bonding inductance. The maximum gain and 3-dB down bandwidth of the equalizing amplifier IC's are 64 dB and 1.2 GHz, respectively. The noise figure obtained is 4.5 dB within the dc to 2-GHz range.     

High-speed demonstration of an output interface driver forsingle-flux quantum systems

The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm² standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s     

一种衬底波纹注入的宽频带高PSR无片外电容LDO

基于40 nm CMOS工艺,设计了一种具有高频高电源抑制(PSR)的无片外电容 低压差线性稳压器(LDO)电路。电路采用1.1 V电源供电,LDO输出电压稳定在0.9 V。仿真结果表明,传统无片外电容LDO电路的PSR将会在环路的单位增益 频率(UGF)处上升到一个尖峰,之后才经输出节点处的电容到地的通路开始降低,最高时PSR甚至大于0 dB。采用新型的衬底波纹注入技术的LDO能很好地抑制PSR的尖峰,可以做到全频段都在-20 dB以上,相比传统结构,尖峰处的PSR提高了20 dB以上。该LDO适用于需要低电压供电的射频电路。     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

High-speed operation of HTS SQUID-array interface circuits with a cryocooler

The authors evaluated the operation of high-temperature superconducting quantum interference device (SQUID)-array interface circuits (IFCs) with normal-metal control lines. Transimpedance amplification was obtained at an operating speed of 1 Gb/s using a cryocooler. The effect of the number of SQUIDs connected in series and the number of arrays connected in parallel on the level of output from the SQUID-array IFCs was examined by Josephson circuit simulation, and then the effect of statistical spreads of junction characteristics was evaluated by Monte Carlo simulation. It was found that the configuration of two parallel SQUID arrays with 64 SQUIDs gives the highest output when the junction characteristics in the arrays have a certain spread. The authors fabricated the IFCs by using the conventional interface-engineered junction process. The process reproducibility was 100 /spl mu/A /spl plusmn/25% for junction I/sub c/, and 3.02 pH /spl plusmn/5% and 2.57 pH /spl plusmn/17% for the sheet inductance of the upper and lower electrodes, respectively. The transimpedance at low frequencies reached 20 and 4 V/A for input levels of 20 and 100 /spl mu/A, respectively. Output voltages as high as 4.4 mV at 4.2 K and 2.3 mV at 40 K were obtained. Furthermore, an output voltage of 600 /spl mu/V was obtained for a 1-Gb/s 2/sup 15/-1 pseudo-random binary signal input at 40 K.     

Complementary Josephson junction devices and circuits: a possiblenew approach to superconducting electronics

We present a superconducting logic family whose operation relies on the availability of a current gain greater than one, based on the analogy to semiconductor complementary metal-oxide-semiconductor (CMOS) logic family. The Complementary Josephson Junction (CJJ) logic family utilizes two types of nonlatching devices: a conventional device and a complementary device. The conventional device has a finite critical current, and the complementary device has zero critical current with no input applied. When the input is high, the complementary device has a finite critical current, while the conventional device has zero critical current. The bias current can be steered between a branch with a complementary device and a branch with a conventional device performing logic (and memory) functions. We can also use a resistor as a load to a complementary device. We call this circuit topology the Resistor Complementary Josephson Junction (RCJJ) family. It is analogous to the semiconductor PMOS/resistor logic family. In this paper, we investigate methods of realizing complementary devices, and we present a preliminary analysis of speed, margins, and power dissipation in simple CJJ and RCJJ inverter circuits     

New Delay-Time Measurements on a 64-kb Josephson–CMOS Hybrid Memory With a 600-ps Access Time

A 64-kb subnanosecond Josephson–CMOS hybrid random-access memory (RAM) has been developed with ultrafast hybrid interface circuits. The hybrid memory is designed and fabricated using a commercial 0.18- $muhbox{m}$ CMOS process and NEC-SRL's 2.5- $hbox{kA/cm}^{2}$ Nb process for Josephson circuits. The millivolt-level Josephson signals are amplified to volt-level CMOS digital signals by a hybrid interface amplifier, which is the most challenging part of the memory system. The performance of this amplifier is optimized by minimizing its parasitic capacitance loading. The 4-K operation of short-channel CMOS devices and circuits is reviewed, and a complete 4-K CMOS BSIM3 model, which has been verified by experiments, is discussed. The memory bit-line output currents are detected by ultralow-power high-speed Josephson devices. Here, we report the first high-frequency access-time measurements on the full critical path showing 600 ps for a single bit. We discuss future designs made to reduce the crosstalk and improve margins, as well as plans to reduce power dissipation and latency.      

Optical homodyne receiver based on an improved balance phase-lockedloop with the date-to-phaselock crosstalk suppression

An improved balanced phase-locked loop (PLL) with postdetection processing is proposed to eliminate the data-to-phaselock crosstalk which potentially limits the usable ratio of laser linewidth to bit rate in pilot-carrier phase-shift keying (PSK) optical homodyne systems. The phase-lock current is first subtracted from the output signal of the data receiver before input to the loop filter. An attenuator is used to ensure the equilibrium of the feedback output signal and data-to-phaselock crosstalk. A shaping filter is introduced to simulate the distortion of data signals at the output of the preamplifier. The homodyne receivers based on this kind of PLL have the advantage of a large tolerance for the laser linewidth compared with the conventional balanced PLL receivers     

GaAs/AlGaAs多量子阱FET-SEED灵巧象元

将GaAs／AlGaAs多量子阱光探测器、光调制器与GaAs场效应晶体管（FET）混合集成,构成FET-SEED灵巧象元。光探测器和光调制器均为反射型自电光效应器件（SEED）,光源为骨子阱半导体激光器。测出的光输出Pout／光输入Pin特性表明,光输入信号对光输出信号有明显的调制作用,光输入信号较小的变化可以导致光输出信号较大的变化。