Josephson edge-triggered gates for sequential circuits

A Josephson sequential logic family with a very wide operating margin (±67%) and insensitivity to global parameter variations is proposed. Derived from the original idea of the edge-triggered latching comparator by C. Hamilton et al. (see IEEE Trans Magnetics, vol.MAG-21, p.197-9, 1985), this logic gate consists of a pair of conventional gates in series biased by a delay clock. In normal operation, switching occurs in one and only one of the gates, depending on which one has the smaller critical current. The authors have built and tested a few circuits to illustrate this logic gate design: a 32-b shift register designed by OR gates with ±42% bias margin and ±89% input margin, a 4-b pseudorandom sequence generator designed by exclusive-OR gates with ±27% bias margin and ±78% input margin, and cross section of a 6-b NOR gate decoder with ±33% bias margin     

Planariation technology for Josephson integrated circuits

Planarization technology has enabled completion of the multi-level layer structure, which is essential to the achievement of large-scale integration and high-speed operation. A new etch-back planarization technology, using 2000-molecular weight polystyrene, has been developed for Josephson integrated circuits (IC's). This technology has been applied to fabricating the multilevel layer structure in magnetic coupled gates. The results, indicated by their cross-sectional SEM photographs and measured breakdown voltages, show that excellent planarity was achieved in this structure     

All-refractory Josephson logic circuits

A process for the fabrication of Josephson integrated circuits is described which uses only refractory materials. The Josephson devices are Nb-Si-Nb tunnel junctions which are formed in the initial phase of the process. After depositing a Nb-Si-Nb `trilayer' over the entire substrate, the individual devices are isolated by the selective niobium anodization process (SNAP). Other materials used are molybdenum for the normal resistors and bias-sputtered SiO/SUB 2/ for additional insulator layers. The process uses only five photolithographic steps to produce circuits of the direct-coupled isolation type. This simplicity is achieved by using some layers for multiple purposes and by fabricating components with different functional purposes in a single step. For example, the lower electrode of the Josephson devices also functions as the ground plane and the contacts to the ground plane are actually large-area Josephson junctions formed simultaneously with the active devices. Low capacitance junctions (~0.025 pF//spl mu/m/SUP 2/) are produced with good uniformity.     

Self-biasing Josephson logic circuits

A self-biasing network for Josephson logic circuits that permits wide variations in junction critical currents, resistors, and power supply voltage is presented. The self-biasing network automatically switches resistors in or out to make the gate currents track with the critical currents of the logic gates. Results of Monte Carlo statistical analyses of the tolerances of this scheme are presented as a function of amount of correlation between the critical currents of the logic device and the biasing network, amount of systematic variation on a chip, and number of junctions used in the biasing network. Results indicate that almost a factor of two larger variations in the critical currents of the Josephson junctions can be tolerated when the self-biasing network is used, without adverse impact on the gate delays and the power dissipation.     

Josephson nonlatching logic circuits

The authors describe nonlatching logic circuits that can be designed using Josephson junctions as the switching elements. The circuits require no current resetting and can be switched between their two logic states with a subnanosecond delay time. The switching behavior has been simulated numerically. The choice of parameters and junction types is analyzed. The distinctive features which make these circuits attractive are discussed.     

High-reliability Pb-alloy Josephson junctions for integrated circuits

The process developed and recently used at IBM for fabricating experimental Pb-alloy Josephson tunnel-junction devices, and the factors which influence the stability of such devices during repeated cycling between 300 and 4.2 K are reviewed. A new, fine-grained Pb0.84In0.12Au0.04alloy base electrode material has been developed that has excellent thermal cycling stability. In an experiment carried out to evaluate the cyclability of devices prepared with this material, excellent results were obtained: the cyclability of large-area junctions was improved by ∼100× compared to that of similar junctions prepared with the recently used, larger-grained Pb0.84In0.12Au0.04base electrodes. In the best cases, populations of 2600 large junctions and 2350 interferometers were found to withstand 400 and 700 thermal cycles to 4.2 K, respectively, before the first failures were observed. These results indicate that with the use of fine-grained electrodes, Pb-alloy Josephson devices have good potential for meeting the cycling requirements of computer systems.     

Higher-order statistics-based input/output system identification and application to noise cancellation

Higher-than-second-order statistics-based input/output identification algorithms are proposed for linear and nonlinear system identification. The higher-than-second-order cumulant-based linear identification algorithm is shown to be insensitive to contamination of the input data by a general class of noise including additive Gaussian noise of unknown covariance, unlike its second-order counterpart. The nonlinear identification is at least as optimal as any linear identification scheme. Recursive-least-squares-type algorithms are derived for linear/nonlinear adaptive identification. As applications, the problems of adaptive noise cancellation and time-delay estimation are discussed and simulated. Consistency of the adaptive estimator is shown. Simulations are performed and compared with the second-order design.Part of the results of this paper were presented at the workshop on HOSA, Vail, CO, June 1989, and at the International Conference on ASSP, Albuquerque, NM, April 1990. The work of G. B. Giannakis in this paper was supported by LabCom Contract 5-25254.     

Equalizers for multiple input/multiple output channels and PAMsystems with cyclostationary input sequences

The author studies minimum mean square error (MMSE) linear and decision feedback (DF) equalisers for multiple input/multiple output (MIMO) communication systems with intersymbol interference (ISI) and wide-sense stationary (WSS) inputs. To derive these equalizers, one works in the D-transform domain and uses prediction theory results. Partial-response MMSE equalizers are also found. As an application, the author considers a pulse amplitude modulation (PAM) communication system with ISI and cyclostationary inputs. The MMSE linear and DF equalizers are determined by studying an equivalent MIMO system. The resulting filters are expressed in compact matrix notation and are time-invariant, whereas the corresponding single input/single output filters are periodically time-invariant. The author also considers MMSE equalizers for a wide-sense stationary process by introducing a `random phase'. To aid in the performance evaluation of various equalizers, the author derives their mean square errors     

An efficient method for finding DC solutions for Josephson circuits

The formulation of Josephson circuit equations in the DC state is discussed and a mixed-mode approach that combines the nonlinear solution method of source-stepping and time-domain method of numerical integration is proposed. Since Josephson circuit equations are often multivalued, the mixed-mode algorithm follows the paths of the independent sources, detects ill-conditioned points, and converges to stable points on the characteristic curves of the simulated circuit. The algorithm uses a combination of source stepping and transient calculation with resistive damping. An adaption of method to superconducting quantum interference device (SQUID) threshold curve calculation is also discussed. The techniques are suitable and presented in sufficient detail, so that a reader may implement them as part of a general simulation program such as JSIM or SPICE     

Chip-to-chip driver and receiver circuits for a Josephson computer

Requirements for drivers and receivers in a Josephson computer are described for transmission of logic signals over long lines and through package connectors. A driver with noise protection and rise time control for smooth propagation through inductive discontinuities has been designed. The receiver design incorporates polarity discrimination for rejection of signals stored on a long line. Drivers and receivers were fabricated, polarity discrimination was demonstrated, and delays were measured and found to agree with simulations. Nominal driver-receiver delay is 160 ps.     

A rail-to-rail input/output CMOS power amplifier

A rail-to-rail amplifier that maintains a high common-mode rejection ratio (CMRR) over the whole common-mode range and has a low harmonic distortion despite the use of relatively small output devices is discussed. The circuit, which measures only 0.3 mm² in a 3-μm technology, has a quiescent current consumption of 600 μA and a CMRR larger than 55 dB. It handles up to 4 nF, and can, with a 5-V supply, drive 3.8 V_pp into 100 Ω (0.1% total harmonic distortion at 10 kHz)     

Touch display?a novel input/output device for computers

A novel input/output device for computer systems has wires, sensitive to the touch of a finger, on the face of a cathode-ray tube on which information can be written by the computer. This device, the `touch display?, provides a very efficient coupling between man and machine.     

New input/output designs for high speed static CMOS RAM

New input and output schematics and optimum design for cell and array are proposed, and applied to a 256/spl times/4 bit CMOS static RAM. Simplified decoder circuit with effective decoder control circuit has a high speed and a wide timing margin. Simple sense amplifier and compact output circuit bring higher speed and reduction in pattern area. Using p-channel transfer gate for memory cell and array, the switching speed and operational stability are much improved. The device is fabricated by 5 /spl mu/m layout rule Si-gate CMOS technology. An 80 ns access time and 100 ns minimum cycle time are acquired at 5 V supply. Power dissipation is less than 7.5 mW at 1 MHz operation.     

`Bootstrapping? in Josephson tunnelling logic circuits

`Bootstrapping? in Josephson tunnelling logic circuits has been realised by providing series connection of multiple junctions and feedback of output current as an additional control current. Computer simulations have demonstrated that the speed-up of the circuits is successfully achieved. This configuration is effective for high-fanout logic circuits, memory peripheral circuits, etc.     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

Novel bipolar differential input/output current-controlled current source

A new bipolar differential input/output current-controlled current source (CCCS) is described. The basic cell consists of a translinear array of six transistors with two bipolar inputs, and is suited for the input stage of a differential current-mode operational amplifier.     

Partial input/output decoupling in time-delay control systems

The decoupling problem is considered for a class of multi-input multi-output time-delay systems, the parameters of which do not satisfy the conditions for total decoupling, i.e. the conditions for decouplin all input/output pairs. It is shown that in this case it is possible to decouple number of input/output pairs equal to the rank of the decoupling matrix. The partial decoupling procedure is illustrated by means of an example.     

Reduction of the input current harmonic content in matrixconverters under input/output unbalance

This paper deals with the performance evaluation of space-vector-modulated matrix power converters under input and output unbalanced conditions. Two control strategies of the input current displacement angle are presented and compared in order to emphasize their influence on the input current harmonic content. The first is based on keeping the input current vector in phase with the input voltage vector. In the second, the input current displacement angle is dynamically modulated as a function of positive- and negative-sequence components of the input voltages. In both cases, the harmonic content and the three-phase RMS value of the input current have been evaluated analytically. The input current harmonic spectrum is quite different for the two control strategies and can be related to the input and output unbalance. It has been verified that, in the usual case of balanced output conditions, using the second method, it is possible to eliminate the harmonic components of the input current. Some numerical simulations are presented to confirm the analytical results