Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result in malfunctioning of circuits, either due to complexity of digital circuits or due to interaction with software. A fault-tolerant scheme such as triple-modular redundancy (TMR) is being implemented increasingly in digital systems. One of the drawbacks of this scheme is that the reliability of the voter circuit is assumed to be very high, which may not be true. Most of the implementation of digital circuits is in the form of integrated circuit; so all the circuit elements are fabricated with same technology and hence reliability of all the components is usually same. In this paper we are presenting a novel fault-tolerant voter circuit which itself can tolerate a fault and give error free output by improving the overall system’s reliability.     

Design and DCVS implementation of a self-checking bus-monitor unitfor highly reliable fault-tolerant system configurations

We present the design and implementation of a bus-monitor unit targeted for the design of highly reliable fault-tolerant systems. The bus-monitor is designed using differential cascode voltage switch (DCVS) logic, whose inherent characteristics result in self-checking circuits. It is implemented in an application specific integrated circuit that can be used to implement a variety of fault-tolerant architectures including triple modular redundant and hybrid configurations. The unit is capable of detecting and correcting failures in the redundant modules by monitoring their respective buses, and it delivers fault-free data to the destination modules. The unit is also capable of detecting faults occurring in the unit itself by utilizing the fault secure properties of DCVS logic. In this paper, we present the operation of the bus-monitor unit and we describe its DCVS design and implementation, as well as the performance characteristics of the prototype chips. Finally, we illustrate how the bus-monitor unit(s) can be used to implement highly reliable fault-tolerant architectures, and we demonstrate that architectures designed using the developed unit(s) exhibit higher reliability compared to the ones implemented with CMOS logic, using the same number of computational resources     

具有在线修复能力的强容错三模冗余系统设计及实验研究

 为提高太空恶劣环境中电子系统的可靠性,提出了一种具有芯片级在线修复能力的强容错三模冗余(TMR)系统结构及设计方法,可在不影响系统正常工作的前提下实现故障模块的在线修复.该系统采用TMR结构,可实时检测定位故障模块;模块采用组件备份法设计,故障发生时可通过备件切换法快速自修复,模块中每个故障组件均可通过进化进行修复;并通过异构冗余降低2个以上模块同时故障的概率.以具有片内三模冗余的三阶高密度双极性(HDB3)编码器系统设计为例,对系统结构和各种容错修复机制进行了验证,结果表明系统可靠性得到很大提高.     

History Index of Correct Computation for Fault-Tolerant Nano-Computing

Future nanoscale devices are expected to be more fragile and sensitive to external influences than conventional CMOS-based devices. Researchers predict that it will no longer be possible to test a device and then throw it away if it is found to be defective, as every circuit is expected to have multiple hard and soft defects. Fundamentally new fault-tolerant architectures are required to produce reliable systems that will survive with manufacturing defects and transient faults. This paper introduces the History Index of Correct Computation (HICC) as a run-time reconfiguration technique for fault-tolerant nano-computing. This approach identifies reliable blocks on-the-fly by monitoring the correctness of their outputs and forwarding only good results, ignoring the results from unreliable blocks. Simulation results show that history-based TMR modules offer a better response to fault tolerance at the module level than do conventional fault-tolerant approaches when the faults are nonuniformly distributed among redundant units. A correct computation rate of 99% is achieved despite a 13% average injected fault rate, when one of the redundant units and the decision unit are fault-free as well as when both have a low injected fault rate of 0.1%. A correct computation rate of 89% is achieved when faults are nonuniformly distributed at an average fault rate of 11% and fault rate in the decision unit is 0.5%. The robustness of the history-based mechanism is shown to be better than both majority voting and a Hamming detection and correction code.      

Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

Microcomputer system reliability using triple-modular redundancy (TMR) is discussed when failures exist not only in any single module but also in any two or three modules at a time. The optimal time interval is calculated by which the system will even be resynchronized periodically so that additional transient failures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU's.     

基于关键路径的三模冗余表决器插入算法

在FPGA的三模冗余设计中,寄存器的反馈环路会导致错误持续出现,严重影响三模冗余的容错性能,因此需要在寄存器的反馈环路上插入表决器。该文首次提出了一种针对映射后网表进行三模冗余设计的方法,同时提出了基于关键路径的表决器插入算法,该算法在表决器的插入时避开关键路径,缓解了三模冗余设计中插入表决器时增加延时的影响。与国外同类算法相比,该文算法在不降低电路可靠性的前提下,以不到1%的面积开销,使得关键路径延时减少3%~10%,同时算法运算速度平均提高35.4%。     

一种具有TSC功能的TMR系统表决器设计方法

本文给出了一种具有完全臬校验功能的三模冗余系统表决器的设计方法。与以往有关ＴＭＲ自温度方面的研究相比，此电路是完全自校验的，它直接将表决器做成完全自校验的，不用在系统外另加冗余四阶累积量适于ＶＬＳＩ实现，此设计思想很容易扩展成Ｎ模冗余系统完全自校验表决器的设计。     

Progressive module redundancy for fault-tolerant designs in nanoelectronics

Redundancy techniques are widely used to increase the reliability of the circuits. This paper proposes an efficient method to select the best subset among possible redundant architectures. It builds upon the progressive module redundancy technique and the block grading concept. Furthermore, this method is not constrained on TMR but extends to 5MR. Experiment results demonstrate its advantages in efficiency, reliability and cost. The proposed method points out a new direction of economical redundant fault-tolerant designs for nanoelectronics.     

On Optimal Redundancy of Multivalue-Output Systems

This paper considers improving the reliability of multivalue-output systems by the use of n-redundant systems in which n copies of systems are used redundantly and the output is determined from the outputs of those copies by the voter. A k-out-of-n redundant system minimizes the mean loss caused by the occurrence of output errors under the condition that the voter can be composed of only two kinds of operators, logical sum and logical product. The optimal k depends on the probability and loss matrices, but it can be specified in some special cases. The mean loss of multivalue-output systems with multichannels can be minimized by adopting k-out-of-n redundancy for each channel. The results provide a powerful guide to the improvement of fail-safe characteristics of many systems and the design of fault-tolerant systems.     

Low-power fault-tolerant interconnect method based on LCDMA and duplication

High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased by using hardware redundancy, and three LCDMA-based fault tolerant designs are proposed: (a) duplication with logic comparison (DLC), (b) conventional triple modular redundancy (TMR), and (c) triple modular redundancy with sign voter (TSV). With aim to detect a received bit from chip sequence, LCDMA–DLC and LCDMA–TSV designs compare absolute values of the sums, while LCDMA–TMR compares only sign bits of the sums generated at the outputs of decoders. All proposed designs are implemented in FPGA and ASIC technologies. MATLAB simulation results show that increasing the length of spreading codes affects to an increase in reliability. A comparative analysis of the proposed fault tolerant designs in terms of hardware complexity, latency, power consumption and error detecting and correcting capability is conducted. It is shown that LCDMA–DLC design has lower hardware overhead and power consumption, with satisfactory better bit error rate (BER) performance, in comparison to LCDMA–TMR and LCDMA–TSV approach.     

航管雷达任务管理冗余设计与实现

本文研究了双机冗余系统的容错技术和方法,提出了基于热备份冗余模式的双任务管理系统方案,主要内容包括冗余方案的选择,双任务管理系统的硬件设计和软件设计三个方面.     

Microcomputer reliability improvement using triple-modular redundancy

Triple-modular redundancy (TMR) is a classical technique for improving the reliability of digital systems. However, applying TMR to microcomputer systems may not improve overall system reliability because voter circuits may contribute as much to system unreliability as the microprocessors themselves. We examine the issues that affect the effectiveness of TMR for transient recovery and the reliability of semiconductor memory systems. With careful application, TMR can improve the mission time of a small system by a factor of 3 or more.     

Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy

The aggressively scaled CMOS technology is increasingly threatening the dependability of network-on-chips (NoCs) architecture. In a mesh-based NoC, a faulty router or broken link may isolate a well functional processing element (PE). Also, a set of faulty routers may form isolated regions, which can degrade the design. In this paper, we propose a router-level redundancy (RLR) fault-tolerant scheme that differs from the traditional microarchitecture-level redundancy (MLR) approach to relieve the problem of isolated PE and isolated region. By simply adding one spare router within each router set in a mesh, RLR can be created and connection paths between adjacent routers can be diversified. To exploit this extra resource, two reconfiguration algorithms are demonstrated to detour observed faulty routers/links. The proposed RLR fault-tolerant scheme can tolerate at most one faulty router within a router set. After the reconfiguration, the original mesh topology is maintained. As a result, the proposed architecture does not need any support from the network layer routing algorithms. The scheme has been evaluated based on the three fault-tolerant metrics: reliability, mean time to failure (MTTF), and yield. The experimental results show that the performance RLR increases as the size of NoC grows; however, the relative connection cost decreases at the same time. This characteristic makes our architecture suitable for large-scale NoC designs.

     

N-modular redundancy using the theory of error correcting codes

Using redundancy is basic to fault-tolerant computing. N-modular redundancy (NMR) is in some ways analogous to the use of a repetition code where an information symbol is replicated as parity symbols in a codeword. Linear error-correcting codes (ECC) use linear combinations of information symbols as parity symbols to generate syndromes for error patterns. In this paper, ECC theory has been applied to derive redundant circuits that tolerate faults in both the modules and checkers. Circuits using comparators for diagnosis are derived with a non-graph-theoretic approach. Coding theoretic principles are applied directly to NMR, so that extensive diagnosis of the fault-tolerant system is achieved.     

Design,evaluation and fault-tolerance analysis of stochastic FIR filters

Stochastic computing utilizes compact arithmetic circuits that can potentially lower the implementation cost in silicon area. In addition, stochastic computing provides inherent fault tolerance at the cost of a less efficient signal encoding. Finite impulse response (FIR) filters are key elements in digital signal processing (DSP) due to their linear phase-frequency response. In this article, we consider the problem of implementing FIR filters using the stochastic approach. Novel stochastic FIR filter designs based on multiplexers are proposed and compared to conventional binary designs implemented using Synopsys tools with a 28-nm cell library. Silicon area, power and maximum clock frequency are obtained to evaluate the throughput per area (TPA) and the energy per operation (EPO). For equivalent filtering performance, the stochastic FIR filters underperform in terms of TPA and EPO compared to the conventional binary design, although the stochastic design shows more graceful degradation in performance with a significant reduction in energy consumption. A detailed analysis is performed to evaluate the accuracy of stochastic FIR filters and to determine the required stochastic sequence length. The fault-tolerance of the stochastic design is compared with that of the binary circuit enhanced with triple modular redundancy (TMR). The stochastic designs are more reliable than the conventional binary design and its TMR implementation with unreliable voters, but they are less reliable than the binary TMR implementation when the voters are fault-free.     

Clos-based fault tolerant multicast ATM switch

A Clos-based fault tolerant multicast ATM switch is proposed in which each stage has one more redundant switch module. If one switch module is faulty, the redundant module replaces the faulty module. On the other hand, even under fault-free conditions, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance     

Generation Methodology for Good-Enough Approximate Modules of ATMR

Approximate triple modular redundancy (ATMR) is sought for logic masking of soft errors while effectuating lower area overhead than conventional TMR through the introduction of approximate modules. However, the use of approximate modules instigates reduced fault coverage in ATMR. In this work, we target better design tradeoffs in ATMR by proposing a heuristic method that effectively utilizes a threshold for unprotected input vectors to generate good enough combinations of approximate modules for ATMR, which accomplishes higher fault coverage and reduced area overhead compared with previously proposed approaches. The key concept is to employ logic optimization techniques of prime implicant (PI) expansion and reduction for successively obtaining approximate modules such that the combination of three approximate modules appropriately functions as an ATMR. For an ATMR to function appropriately, blocking is used to ensure that at each input vector, through the prime implicant (PI) expansion and reduction technique, only one approximate module differ from the original circuit. For large circuits, clustering is utilized and comparative analysis indicates that higher fault coverage is attained through the proposed ATMR scheme while preserving the characteristic feature of reduced area overhead. With a small percentage of unprotected input vectors, we achieved substantial decrease in transistor count and greater fault detection, i.e., an improvement of up to 26.1% and 42.1%, respectively.     

三模冗余在ASIC设计中的实现方法

星载计算机系统处于空间辐照环境中,可能会受到单粒子翻转的影响而出错,三模冗余就是一种对单粒子翻转有效的容错技术。通过对三模冗余加固电路特点的分析,提出了在ASIC设计中实现三模冗余的2种方法。其一是通过Syno—psys的综合工具DesignCompiler对原设计进行综合,然后修改综合后的门级网表再次综合;其二是直接建立采用三模冗余加固的库单元。     

Bilateral Testing of Nano-scale Fault-Tolerant Circuits

As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge. In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS’85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses.