Design of CMOS circuits for stuck-open fault testability

A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes     

Testable design of BiCMOS circuits for stuck-open fault detectionusing single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults     

边界扫描技术在板级可测性设计中的应用探索

随着硬件系统的规模不断庞大,其内部精度也逐渐增加,相关的测试工作难度越来越大,在这一过程中应用边界扫描技术则能够较好的解决这一问题。本文主要探讨了边界扫描技术的原理,从设计、优化等各个方便针对边界扫描技术在板级可测性设计中的应用。最终结果提示该技术能够显著降低测试时间,对于提高系统经济价值具有较好的作用。     

诊断权衡优化测试性分析技术

现今对于电子设备进行故障诊断以及后续PHM的需求越来越多,本文结合测试性分析的流程,提出了一种面向诊断的测试性分析方法,并使用开发的软件对某型号的发电机进行测试性建模与分析,按照给出的诊断策略进行测试可以取得比较好的效果。     

Implementation of a self-resetting CMOS 64-bit parallel adder withenhanced testability

This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by self-resetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22°C with V_dd=2.5 V) and 300 mW. The adder core size is 1.6×0.275 mm². The process technology used was the 0.5 μm IBM CMOS5X technology with 0.25 μm effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs     

The economics of scan-path design for testability

In this article, scan design for testability (DFT) methods are categorized based on the percentage of storage elements made scannable. The non-scan element state retention problem that occurs in partial scan design methods, in which not all of the storage elements are implemented as scan elements, is discussed. Solutions to this problem are described and the overheads associated with them are discussed. An economic model that allows the costs of a range of scan methods that differ in the percentage of storage elements made scannable to be compared with each other is presented. It is shown that, for systems produced in low volumes, the adoption of full scan DFT can be more cost-effective than partial scan DFT when life-cycle costs are considered if it results in significant reductions in the time taken to get the product to market.     

A 2.45 GHz CMOS up-conversion mixer design utilizing the current-reuse bleeding technique

A 2.45?GHz double-balanced modified Gilbert-type complementary metal-oxide-semiconductor (CMOS) up-conversion mixer design utilizing the current-reuse bleeding p-channel mos (PMOS) transistors is examined thoroughly based on simulations to demonstrate many advantages achievable when adopting the current-reuse bleeding technique in the mixer design. It is shown that the current-reuse bleeding technique certainly provides benefits in terms of gain, linearity and noise characteristics. In the mixer incorporating the current-reuse bleeding technique, the conversion gain improves monotonically with more bleeding. The linearity also improves with bleeding by a noticeable amount when the voltage headroom is not adequate. However, with excessive bleeding, linearity degrades by the current-limiting phenomena which defines the optimal bleeding ratio. Noise performance also improves monotonically with more bleeding. Of all the benefits provided, the improvement in noise performance seems most valuable. The measurement of the fabricated chip based on the standard 0.35?µm CMOS process supports the validity of the analysis. The measured mixer performance is quite excellent, and the measured characteristics are in close agreement with the simulations, which demonstrates the adequacy of the modelling approach based on the macro models for all the active and passive devices used in the design.     

基于模型的综合模块化航电系统测试性设计方法

针对综合模块化航电系统对测试性提出的更高要求及其工程实践中存在的典型问题,定义了一种分布-集中式的系统测试诊断架构,以适应其体系架构的特点和生产配套关系的变化;提出了一种基于模型的系统测试性设计方法和流程,以测试性模型为驱动指导航电系统的测试性方案设计、评估与优化过程,取代传统的基于指标的测试性设计方法。在某机载综合射频系统上开展了方法应用,成功解决了该系统综合化以后测试诊断架构设计与测试性分配的非线性问题。     

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors.With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome.The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.     

基于小波分析的CMOS电路IDDT故障诊断新技术

对CMOS数字集成电路故障诊断技术的基本方法进行介绍,探讨了基于小波分析的CMOS电路瞬态电流IDDT故障诊断新技术的基本原理和作用。介绍了该故障诊断新技术的国内外研究动态,展望了其在超大规模集成电路的故障诊断、失效机理研究、可靠性提高等方面的作用、意义及其广阔的应用前景。     

TWO-INPUT PRESETTING TECHNIQUE AND DESIGN OF CMOS FLIP-FLOPS WITH A HIGH RADIX

By analysing the difficulty of previous flip-flops with a high radix, this paper proposes a logic design scheme with two presetting inputs. The circuit of a quaternary CMOS flip-flop is designed by using the transmission function theory. The result shows that its structure is simpler and its processing speed is higher than that of two binary flip-flops which store the equal information.     

综合化核心处理平台测试性设计探讨

综合化技术的发展对产品的测试性提出了很高的要求,文章对核心处理平台的测试性设计进行了探讨,重点从机内测试系统、自动测试系统和故障预测与健康管理三方面对测试性设计进行分析.     

Application of a multivariable optimiser to the design of CMOS buffers

A multivariable optimiser is used to individually optimise the size of each stage in a CMOS buffer. Then the optimiser is used to minimise the silicon area for a given buffer delay. An area saving of up to 50% is obtained, compared to other types of buffer.<>     

CMOS design of the tree arbiter element

An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers eager forward-propagation of requests. It compares favorably with a well-known design in which request propagation must wait for arbitration to complete. Our analysis and simulations also suggest that no performance improvement will be obtained by incorporating eager acknowledgment of releases. All of the designs considered in this paper are speed-independent, a formal property of a network of elements which can be taken as a positive indication of their robustness     

A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps<4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30-64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5×0.95 mm².     

A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique

This paper describes the circuit design and measurement results of a new CMOS frequency doubler proposed for 5-GHz-band wireless applications. The doubler, which can operate at 1.8 V, was fabricated in a standard 0.18-/spl mu/m bulk CMOS technology which has no extra processing steps to enhance RF performance. A current-reuse circuit-design technique is successfully incorporated into the doubler so as to realize both on-chip input/output matching and adequate conversion gain with low input power drive despite the utilization of the standard bulk CMOS technology. The doubler with a single input/output interface features a bypass resistor placed between common ground and a source node of the second stage FET in the current-reuse topology, thereby improving both input power level and conversion gain while saving waste current. Measurement results under the condition of 5.2 GHz and 1.8 V reveal the following good performance: a 2.7-dB maximum conversion gain, a 0.3-dBm high output power, and a 9-mA low current dissipation are achieved with a 2.6-GHz, -3-dBm input power. With a 7-mA low current dissipation and a -7-dBm low input power, the doubler can deliver conversion gain as high as 0 dB. These measurement results are good agreement with the simulated ones.     

Process variation aware dual-Vth assignment technique for low power nanoscale CMOS design

This paper presents a novel sensitivity-based, transistor-level, dual threshold voltage (V_th) assignment technique for the design of low power nanoscale CMOS circuits. The proposed technique is based on the Plackett-Burman Design of Experiment method (PB-DOE) in which sensitivity of each transistor to delay variation due to change in its V_th is obtained. The various paths in the circuit are categorized into process sensitive and process-insensitive paths. Transistors in the process sensitive paths are assigned a high V_th to reduce the leakage power without affecting performance. The application of the proposed technique to ISCAS-85 C17 benchmark circuit shows 20% reduction in the leakage power as compared to conventional gate-level dual-V_th assignment technique. Moreover, it is shown that the proposed algorithm can be easily extended to assign dual gate length circuits to achieve a further 20% reduction in the leakage power. The robustness of the proposed technique against process variations is demonstrated with extensive Monte Carlo Simulations. The versatility of the proposed approach to reduce the leakage power for a general CMOS circuit is demonstrated using a Manchester carry chain adder.     

Comments on the optimum CMOS tapered buffer problem

Two recent papers, one by Li et al. (see ibid., vol 25, p1005-8,1990) and the other by Prunty and Gal (see ibid., vol. 27, no. 1, p118-9,1992), on the optimum CMOS tapered buffer problem are commented on. These papers claim that an equivalent “short-circuit” current capacitance should be added to the output capacitance of an inverter to account for the increased propagation delay obtained because of the short-circuit current that flows when a real input waveform is considered instead of an input step voltage. The reasoning results in an optimum tapering factor that is dependent on the waveform rise and fall times. However, the propagation delay only depends on the load capacitance and the ratio of the input to output transition times. In a fixed-taper buffer these transition times are equal making the optimum tapering factor independent of the “short-circuit” current. The comments also suggest an improved method of determining the optimum tapering factor in practical situations based on circuit simulations     

装备固有测试性评价方法研究

固有测试性设计是装备测试性设计的重要内容,在对装备测试性进行验证和评价时,也需要评价其固有测试性。为了解决固有测试性评价方法适用性不强的问题,提出了一种新的装备固有测试性评价方法。在分析固有测试性设计要求的基础上,从检测隔离性能、功能结构划分的合理性、可控性和可观测性四个方面提出了6项评价指标,并利用模糊综合评价模型作为定量分析工具,最终达到量化评价装备固有测试性的目的。为进一步进行装备测试性综合评价或验证奠定了基础。最后通过某型液位传感系统的固有测试性评价实例,验证了该方法的可行性。