Impact of scaling silicon film thickness and channel width on SOIMOSFET with reoxidized MESA isolation

The characteristics of reoxidized MESA isolation for silicon-on-insulator (SOI) MOSFET have been studied in terms of the dependence of device performance on silicon film thickness and channel width scaling. For devices with silicon film thickness (T_Si) smaller than a critical thickness, humps appear in subthreshold IV and negative threshold voltage shift is observed in narrow width devices. The width encroachment (ΔW) also increases rapidly with reducing T _Si. These observations can be explained by the formation of sharp beak and accelerated sidewall oxide growth in these devices. A simple guideline is given to optimize the reoxidation process for different T_Si     

The behavior of narrow-width SOI MOSFETs with MESA isolation

Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

Threshold voltage sensitivity of 0.1 μm channel lengthfully-depleted SOI NMOSFET's with back-gate bias

We found threshold voltage sensitivity to silicon thickness variation in 0.1 μm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior     

Fully-depleted SOI devices with TaSiN gate, HfO/sub 2/ gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.     

Sidewall-related narrow channel effect in mesa-isolatedfully-depleted ultra-thin SOI NMOS devices

The paper reports the sidewall-related narrow channel effect in mesa-isolated fully-depleted ultra-thin SOI NMOS devices. Based on the study, contrary to bulk NMOS devices, for a channel width shrinking from 1 μm to 0.2 μm, the threshold voltage of mesa-isolated ultra-thin SOI NMOS devices with a 1000 Å thin film doped with 10¹⁷ cm^-3, decreases by 0.145 V for a front gate oxide of 100 Å and a sidewall oxide of 150 Å as a result of the sidewall edge effect     

Advanced technologies for optimized sub-quarter-micrometer SOI CMOSdevices

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (~450°C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p⁺SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented     

Three-dimensional analytical subthreshold models for bulk MOSFETs

Three-dimensional device-physics-based analytical models are developed for subthreshold conduction in uniformly doped small geometry (i.e., simultaneously short channel and narrow width) bulk MOSFETs, for various isolation schemes. Inverse-narrow width effects, where the threshold voltage decreases with decreasing channel width, are predicted by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs, conventional narrow width effects, where the threshold voltage increases due to decreasing channel width, are predicted. The narrow width effects are found to be comparable to the short channel effects in the absence of significant applied drain biases. However, for larger drain biases, the short channel effects outweigh the narrow width effects due to the weaker potential perturbation at the device width edges compared to the drain end. Unlike the threshold voltage, the subthreshold swing of the device is found to increase with reduced device dimensions regardless of the isolation scheme since both conventional and inverse narrow width effects result in weaker control of the surface potential by the gate     

对异型硅岛实现的厚膜全耗尽SOIMOSFET的模拟研究

本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间.     

薄膜SOI上大于600 V LDMOS器件的研制

针对600 V以上SOI高压器件的研制需要,分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案,并通过仿真预言其可行性。在埋氧层为3μm,顶层硅为1.5μm的注氧键合(Simbond)SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场,设计了具有线性渐变掺杂60μm漂移区的LDMOS结构。为提高纵向耐压,利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明,器件关态击穿电压可达600 V以上(实测832 V),开态特性正常,阈值电压提取为1.9 V,计算开态电阻为50Ω.mm2。     

全耗尽SOI LDMOS阈值电压的解析模型

通过准二维的方法,求出了全耗尽SOILDMOS晶体管沟道耗尽区电势分布的表达式,并建立了相应的阈值电压模型。将计算结果与二维半导体器件模拟软件MEDICI的模拟结果相比较,两者误差较小,证明了本模型的正确性。从模型中可以容易地分析阈值电压与沟道浓度、长度、SOI硅膜层厚度以及栅氧化层厚度的关系,并且发现ΔVth与背栅压的大小无关。     

Reduction of the reverse short channel effect in thick SOI MOSFET's

We show that the reverse short channel effect (RSCE) is reduced in NMOS devices made in thick silicon-on-insulator (SOI) material. The reduction of the RSCE depends on the thickness of the Si overlayer. It is found that the thinner the Si film, the less the threshold voltage roll-on. The experimental findings are explained by a decrease of the lateral distribution of silicon interstitials generated at the source and drain (S/D) region and are related with their high recombination velocity at the buried oxide. This method can be used to separately test the influence of S/D point defects on the RSCE from other different hypotheses reported in the literature. Coupled process-device simulation reveals that the method is very sensitive to fundamental point defect properties     

Fabrication of gate-all-around transistors using metal inducedlateral crystallization

Gate-all-around transistor (GAT) is demonstrated. The device can be fabricated on either a bulk silicon wafer or on the top of any device layers. The fabrication process used a new technique called metal-induced-lateral-crystallization (MILC) to recrystallize amorphous silicon to form large silicon grains in the active area. Using this technique, the transistor performance is comparable to a SOI MOSFET. Compared with the single-gate thin film transistor (SGT) and solid phase crystallization (SPC) devices, the MILC GAT has lower subthreshold slope, lower threshold voltage, higher transconductance and nearly double drive current, The impact of short channel length was investigated     

Degradation characteristics of STI and MESA-isolated thin-film SOICMOS

I-V degradations of STI (shallow trench isolation) and MESA-isolated SOI are reported for devices with a given threshold voltage design (V_TH≈0.4 V). We show that degradation characteristics of the STI and MESA SOI are quite different from strain-induced degradation observed in LOCOS SOI. It is found that the nMOSFET's I-V degradation becomes more pronounced while pMOSFETs remain relatively constant as the silicon thickness (t_si) is reduced. The reduction of nMOSFET's drive current is attributed to the mobility degradation as the channel concentration is increased, whereas for the pMOSFETs, due to the lesser sensitivity of the hole to the Coulomb scattering, no degradation is observed     

Experimental evidence for quantum mechanical narrow channel effectin ultra-narrow MOSFET's

The authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFET's. Threshold voltage increase is observed at room temperature in ultra-narrow MOSFET's whose channel width is less than 10 nm. This result is in excellent agreement with simulation that takes account of quantum confinement in the silicon narrow channel, indicating that the increase in threshold voltage is caused by the quantum mechanical narrow channel effect     

抑制 SOIp- MOSFET中短沟道效应的 GeSi源 /漏结构

提出在 SOI p- MOSFET中采用 Ge Si源 /漏结构 ,以抑制短沟道效应 .研究了在源、漏或源与漏同时采用 Ge Si材料对阈值电压漂移、漏致势垒降低 (DIBL)效应的影响 ,并讨论了 Ge含量及硅膜厚度变化对短沟道效应及相关器件性能的影响 .研究表明 Ge含量应在提高器件驱动电流及改善短沟道效应之间进行折中选择 .对得到的结果文中给出了相应的物理解释 .随着器件尺寸的不断缩小 ,Ge Si源 /漏结构不失为 p沟 MOS器件的一种良好选择     

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs. Different short channel field effects, such as fringing fields, junction-induced lateral fields and substrate fields, are carefully investigated, and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model. Through analytical model-based simulation, the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations. Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model. The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET. The short channel effects are found to be reduced in an SON, thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope. This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.     

亚100nm SOI器件的结构优化分析

分析了SOI器件各结构参数对器件性能的影响,给出了器件各结构参数的优化方向,找出了可行硅膜厚度和可行沟道掺杂浓度之间的设计容区.在部分耗尽与全耗尽SOI器件的交界处,阈值电压的漂移有一个峰值,在器件设计时应避免选用这一交界区.此外,随着硅膜厚度的减小,器件的泄漏电流随着沟道掺杂浓度的不同,有一个极小值.通过模拟分析发现,只要合理选择器件的结构参数,就能得到性能优良的SOI器件     

Detailed characterization and analysis of the breakdown voltage infully depleted SOI n-MOSFET's

The breakdown voltage in fully depleted SOI n-MOSFET's has been studied over a wide range of film thicknesses, channel dopings, and channel lengths. In lightly-doped films, the breakdown voltage roll-off at shorter channel lengths becomes much less severe as the film thickness is reduced. This is a result of improved resistance to punchthrough and DIBL effects in thinner SOI. Consequently, at channel lengths below about 0.8 μm, ultrathin (50 nm) SOI can provide better breakdown voltages than thicker films. At heavier doping levels the punchthrough and DIBL are suppressed, and there is little dependence of breakdown voltage on film thickness. Two-dimensional simulations have been used to investigate the breakdown behavior in these devices. It is found that the drain-induced barrier lowering affects the breakdown voltage both directly, via punchthrough, and indirectly through its effect on the current flow and hole generation in the high-field regions