Three-State Quantum Dot Gate FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeO _x -cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high-κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeO _x -Ge quantum dots.     

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiO _x -cladded Si or GeO _x -cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO₂. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.     

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II–VI Tunnel Insulators

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn_0.95Mg_0.05S/ZnS tunnel insulators. The GeO _x -cladded Ge and SiO _x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II–VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II–VI stack serves both as a tunnel insulator and a high-κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si₃N₄ and SiO₂ layers grown by plasma- enhanced chemical vapor deposition.     

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

This paper describes the use of II–VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO _x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn_0.95Mg_0.05S-ZnS tunneling layers. The II–VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.     

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeO _x )-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.     

Nonvolatile Silicon Memory Using GeO<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>-Cladded Ge Quantum Dots Self-Assembled on SiO<Subscript>2</Subscript> and Lattice-Matched II–VI Tunnel Insulator

This paper presents fabrication and characterization of a quantum dot-based floating gate nonvolatile memory device with site-specific self-assembly of germanium oxide-cladded germanium (GeO _x -Ge) quantum dots on SiO₂ and ZnS/ZnMgS/ZnS (II–VI lattice-matched high-κ dielectric) tunnel insulator material. These monodispersed and individually cladded quantum dots have the potential to store charge uniformly in the floating gate and are well suited for nonvolatile memory applications.     

Modification of quantum dots in Ge/Si nanostructures by pulsed laser irradiation

The goal of this study was the development of a method for the modification of a quantum dot (QD) structure in Ge/Si nanostructures by pulsed laser irradiation. The Ge_xSi_1?x QD structures were analyzed using data furnished by Raman spectroscopy. Frequency-dependent admittance measurements were used to study the energy spectrum of holes in the Ge/Si heterostructures with Ge_xSi_1?x QDs before and after the laser treatment. The obtained experimental data show that laser treatment makes it possible to reduce the sheet density of QDs, modify their composition, and increase the average size. The most important result is that the QD parameters become more uniform after the treatment with nanosecond laser pulses. In a sample with ODs of 8-nm average lateral size (six monolayers of Ge), the scatter of energy levels in the QD array is reduced by half after the treatment with 10 laser pulses.     

Light-emitting tunneling nanostructures based on quantum dots in a Si and GaAs matrix

InGaAs/GaAs and Ge/Si light-emitting heterostructures with active regions consisting of a system of different-size nanoobjects, i.e., quantum dot layers, quantum wells, and a tunneling barrier are studied. The exchange of carriers preceding their radiative recombination is considered in the context of the tunneling interaction of nanoobjects. For the quantum well-InGaAs quantum dot layer system, an exciton tunneling mechanism is established. In such structures with a barrier thinner than 6 nm, anomalously fast carrier (exciton) transfer from the quantum well is observed. The role of the above-barrier resonance of states, which provides “instantaneous” injection into quantum dots, is considered. In Ge/Si structures, Ge quantum dots with heights comparable to the Ge/Si interface broadening are fabricated. The strong luminescence at a wavelength of 1.55 μm in such structures is explained not only by the high island-array density. The model is based on (i) an increase in the exciton oscillator strength due to the tunnel penetration of electrons into the quantum dot core at low temperatures (T < 60 K) and (ii) a redistribution of electronic states in the Δ₂-Δ₄ subbands as the temperature is increased to room temperature. Light-emitting diodes are fabricated based on both types of studied structures. Configuration versions of the active region are tested. It is shown that selective pumping of the injector and the tunnel transfer of “cold” carriers (excitons) are more efficient than their direct trapping by the nanoemitter.     

High-density formation of Ge quantum dots on SiO2

We formed high-density Ge quantum dots (QDs) on an ultrathin SiO₂ layer by controlling the early stages of low-pressure chemical vapor deposition (LPCVD) with a germane gas (GeH₄) assisted by a remote plasma of pure H₂. We then characterized the electronic charged states of the QDs by an AFM/Kelvin probe technique. The formation of single crystalline Ge-QDs with an areal dot density of ∼2.0 × 10¹¹ cm⁻² was confirmed after examining the surface morphology and lattice by atomic force microscopy and transmission electron microscopy, respectively. It has been suggested that an increase in the flux of deposition precursors due to efficient decomposition of GeH₄ by a supply of hydrogen radicals and the dehydration reaction of surface OH bonds plays a role in nucleation of Ge-QDs on SiO₂. Surface passivation with hydrogen may also promote the surface migration of deposition precursors during LPCVD. The surface potential of the dots changed in a stepwise manner with respect to the tip bias due to multistep electron injection into and extraction from the Ge-QDs.     

Lateral photoconductivity of multilayer Ge/Si structures with Ge quantum dots

Spectra of lateral photoconductivity of multilayer Ge/Si structures with Ge quantum dots, fabricated by molecular-beam epitaxy are studied. The photoresponse caused by optical transitions between hole levels of quantum dots and Si electronic states was observed in the energy range of 1.1–0.3 eV at T = 78 K. It was shown that the electronic states localized in the region of Si band bending near the Ge/Si interface mainly contribute to lateral photoconductivity. The use of the quantum box model for describing hole levels of quantum dots made it possible to understand the origin of peaks observed in the photoconductivity spectra. A detailed energy-level diagram of hole levels of quantum dots and optical transitions in Ge/Si structures with strained Ge quantum dots was constructed.     

Core–Shell ZnxCd1?xSe/ZnyCd1?ySe Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn _y Cd_1−y Se-cladded Zn _x Cd_1−x Se quantum dots (y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn _y Cd_1−y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II–VI quantum dots as well as two diverse types of devices are presented in this paper.     

Low-temperature formation of self-assembled Ge quantum dots on Si(100) under high carbon mediation via solid-phase epitaxy

CMOS-compatible low-temperature formation of self-assembled Ge quantum dots (QDs) by carbon (C) mediation via a solid-phase epitaxy (SPE) has been demonstrated. The samples were prepared by a solid-source molecular beam epitaxy (MBE) system. C and Ge were successively deposited on Si(100) at 200 °C and Ge/C/Si heterostructure was annealed in the MBE chamber. Sparse Volmer-Weber mode Ge dots without a wetting layer were formed for C coverage (θ_C) of 0.25 and 0.5 ML by lowering SPE temperature (T_S) to 450 °C, but small and dense Stranski-Krastanov (SK)-mode Ge QDs with the wetting layer were obtained with increasing C coverage of 0.75 ML even at 450 °C. From the investigation of SPE temperature effect on Ge QD formation for θ_C of 0.75 ML, SK-mode Ge QDs of about 10 nm in diameter and of about 4.5×10¹¹ cm⁻² in density were formed at T_S≥400 °C. The wetting layer of SK-mode QDs was almost constant 0.2-nm thick at T_S≥450 °C. Measurements of chemical binding states of C in Ge QDs and at Ge/Si interface revealed that a large amount of C–Ge bonds were formed in the wetting layer for high C coverage, and the formation of C–Ge bonds, together with the formation of C–Si bonds, enabled the low-temperature formation of small and dense Ge QDs. These results suggest that the C-mediated solid-phase epitaxy is effective to form small and dense SK-mode QDs at low temperature.     

Lateral photoconductivity of Ge/Si heterostructures with Ge quantum dots

The spectral dependences of the lateral photoconductivity of Ge/Si heterostructures with Ge quantum dots are studied. The photoresponse of the Ge/Si structures with Ge nanoclusters is detected in the range 1.0–1.1 eV at T = 290 K, whereas the photocurrent in the single-crystal Si substrate is found to be markedly suppressed. This result can be attributed to the effect of elastic strains induced in the structure on the optical absorption of Si. At temperatures below 120 K, the heterostructures exhibit photosensitivity in the spectral range 0.4–1.1 eV, in which the Si single crystal is transparent. The photocurrent in this range is most likely due to the transitions of holes from the ground states localized in the quantum dots to the extended states of the valence band.     

Ge/Si photodiodes with embedded arrays of Ge quantum dots forthe near infrared (1.3–1.5 µm) region

A method has been devised for MBE fabrication of p-i-n photodiodes for the spectral range of 1.3–1.5 µm, based on multilayer Ge/Si heterostructures with Ge quantum dots (QDs) on a Si substrate. The sheet density of QDs is 1.2×10¹² cm^?2, and their lateral size is ～8 nm. The lowest room-temperature dark current reported hitherto for Ge/Si photodetectors is achieved (2×10^?5 A/cm² at 1 V reverse bias). A quantum efficiency of 3% at 1.3 µm wavelength is obtained.     

Ge-nanocluster formation in Ge-doped polysilicon films under oxidation and heat treatment

An experimental investigation is conducted into the formation Ge nanoclusters by heat treatment of germanosilicate-glass (Si _x Ge _y O _z ) films that are produced by oxidation of Ge-doped nanostructured polysilicon. It employs Auger and IR spectroscopy, high-resolution electron microscopy, and x-ray diffraction. The process by which Ge atoms in the films are transported toward the substrate is found to include the following stages: (1) the formation of a GeO₂ and a SiO₂ phase, (2) the reduction of GeO₂ to Ge by Si, (3) Ge-crystallite nucleation, and (4) Ge-crystallite growth. Heat treatment in humid oxygen at ≥ 800°C is found to increase Ge-nanocluster size, the point of crystallization being 500°C. It is established that heat treatment at a temperature close to the Ge melting point results in complete aggregation of the germanium into clusters, with a twofold increase in both the mean size and the number of clusters. Germanium is found to accumulate at the interface between oxidized and unoxidized polysilicon.     

Nanocrystalline Ge synthesis by the chemical reduction of hydrothermally grown Si0.6Ge0.4O2

Previously, we have reported the use of high pressure oxidation techniques for the growth of compositionally congruent oxides from Si_1−xGe_x. We have now used this technique as part of a two-step process of oxidation at 25 MPa and 475°C followed by reduction in 0.1 MPa (1 atm) H₂ at 700-850δC for the synthesis of nanocrystalline Ge precipitates. Using transmission electron microscopy, we show that the proposed method produces a dispersion of fine (<10 nm) precipitates of Ge embedded in an SiO₂ matrix. The structure of the oxide prior to reduction with H₂ was investigated with Fourier transform infrared spectroscopy which reveals SiO₂, GeO₂, SiO, Si-O-H, and Ge-O-H bonding states in the glass. In this paper, we discuss the thermodynamics and kinetics of both the hydrothermal oxidation technique and the proposed Ge nanocrystalline synthesis process.     

Improved nanocrystal formation,quantum confinement and carrier transport properties of doped Si quantum dot superlattices for third generation photovoltaics

An all‐Si tandem solar cell has the potential to achieve high conversion efficiency at low cost. However, the selection and synthesis of candidate material remain challenging. In this work, we show that the conventional ‘Si quantum dots (Si QDs) in SiO₂ matrix’ approach can lead to the formation of over‐sized Si nanocrystals especially when doped with phosphorous, making the size‐dependent quantum confinement less effective. Also, our investigation has shown that the high resistivity of this material has become the performance bottleneck of the solar cell. To resolve these matters, we propose a new design based on Si QDs embedded in a SiO₂/Si₃N₄ hybrid matrix. By replacing the SiO₂ tunnel barriers by the Si₃N₄ layers, the new material manages to constrain the growth of doped Si QDs effectively and enhances the apparent band gap, as shown in X‐ray diffraction, Raman, photoluminescence and optical spectroscopic measurements. Besides, electrical characterisation on Si QD/c‐Si heterointerface test structures indicates the new material possesses improved vertical carrier transport properties. Copyright © 2011 John Wiley & Sons, Ltd.