Low-Roughness Plasma Etching of HgCdTe Masked with Patterned Silicon Dioxide

A novel mask technique utilizing patterned silicon dioxide films has been exploited to perform mesa etching for device delineation and electrical isolation of HgCdTe third-generation infrared focal-plane arrays (IRFPAs). High-density silicon dioxide films were deposited at temperature of 80°C, and a procedure for patterning and etching of HgCdTe was developed by standard photolithography and wet chemical etching. Scanning electron microscopy (SEM) showed that the surfaces of inductively coupled plasma (ICP) etched samples were quite clean and smooth. Root-mean-square (RMS) roughness characterized by atomic force microscopy (AFM) was less than 1.5 nm. The etching selectivity between a silicon dioxide film and HgCdTe in the samples masked with patterned silicon dioxide films was greater than 30:1. These results show that the new masking technique is readily available and promising for HgCdTe mesa etching.     

HgCdTe干法刻蚀的掩模技术研究

文章报道了HgCdTe微台面列阵ICP干法刻蚀掩模技术研究的初步结果。首先采用常规光刻胶作为HgCdTe材料的ICP干法刻蚀掩模。扫描电镜结果发现，由于刻蚀的选择比低，所以掩模图形退缩严重，刻蚀端面的平整度差，台面侧壁垂直度低。因此采用磁控溅射生长的SiO2掩模进行了相同的HgCdTe干法刻蚀。结果发现，SiO2掩模具有更高的选择比和更好的刻蚀端面。但是深入的测试表明，介质掩模的生长对HgCdTe表面造成了电学损伤。最后通过优化生长条件，获得了无损伤的磁控溅射生长SiO2掩模技术。     

Hierarchically Ordered Arrays of Noncircular Silicon Nanowires Featured by Holographic Lithography Toward a High‐Fidelity Sensing Platform

A novel, highly uniform and tunable hybrid plasmonic array is created via ion‐milling, catalytic wet‐etching and electron‐beam evaporation, using a holographically featured structure as a milling mask. A simple and low‐cost prism holographic lithography (HL) technique is applied to create an unprecedentedly coordinated array of elliptic gold (Au) holes, which act as the silicon (Si) etching catalyst in the reaction solution used to fabricate an elliptic silicon nanowire (SiNW) array; here, the SiNWs are arrayed hierarchically in such a way that three SiNWs are triangularly coordinated, and the triangles are arranged hexagonally. After removing the polymeric mask and metal thin film, the highly anisotropic thick Au film is deposited on the SiNW arrays. This hybrid substrate shows tunable optical properties in the near‐infrared (NIR) region from 875 nm to 1030 nm and surface‐enhanced Raman scattering (SERS) activities; these characteristics depend on the catalytic wet etching time, which changes the size of the vertical gap between the Au thick films deposited separately on the SiNWs. In addition, lateral interparticle coupling induces highly intensified SERS signals with good homogeneity. Finally, the Au‐capped elliptical SiNW arrays can be hierarchically patterned by combining prism HL and conventional photolithography, and the highly enhanced fluorescence intensity associated with both the structural effects and the plasmon resonances is investigated.     

Inductively Coupled Plasma-Induced Electrical Damage on HgCdTe Etched Surface at Cryogenic Temperatures

Plasma etching is a powerful technique for transferring high-resolution lithographic patterns into HgCdTe material with low etch-induced damage, and it is important for fabricating small-pixel-size HgCdTe infrared focal plane array (IRFPA) detectors. P- to n-type conversion is known to occur during plasma etching of vacancy-doped HgCdTe; however, it is usually unwanted and its removal requires extra steps. Etching at cryogenic temperatures can reduce the etch-induced type conversion depth in HgCdTe via the electrical damage mechanism. Laser beam-induced current (LBIC) is a nondestructive photoelectric characterization technique which can provide information regarding the vertical and lateral electrical field distribution, such as defects and p–n junctions. In this work, inductively coupled plasma (ICP) etching of HgCdTe was implemented at cryogenic temperatures. For an Ar/CH₄ (30:1 in SCCM) plasma with ICP input power of 1000 W and RF-coupled DC bias of ～ 25 V, a HgCdTe sample was dry-etched at 123 K for 5 min using ICP. The sample was then processed to remove a thin layer of the plasma-etched region while maintaining a ladder-like damaged layer by continuously controlling the wet chemical etching time. Combining the ladder etching method and LBIC measurement, the ICP etching-induced electrical damage depth was measured and estimated to be about 20 nm. The results indicate that ICP etching at cryogenic temperatures can significantly suppress plasma etching-induced electrical damage, which is beneficial for defining HgCdTe mesa arrays.     

Processing and characterization of a-Si:H photoresists for a vacuum-compatible photolithography process

The vision of achieving a completely in-vacuum process for fabricating HgCdTe detector arrays is contingent on the availability of a vacuumcompatible photolithography technology. One such technology for vacuum photolithography involves the use of amorphous-hydrogenated Si (a-Si:H) as a photoresist. In this work, we deposit a-Si:H resists via plasma-enhanced chemical-vapor deposition (PECVD) using an Ar-diluted silane precursor. The resists are then patterned via excimer laser exposure and development etched in a hydrogen plasma where etch selectivities between unexposed and exposed regions exceed 600:1. To determine the best conditions for the technique, we investigate the effects of different exposure environments and carry out an analysis of the a-Si:H surfaces before and after development etching. Analysis via transmission electron microscopy (TEM) reveals that the excimer-exposed surfaces are polycrystalline in nature, indicating that the mechanism for pattern generation in this study is based on melting and crystallization. To demonstrate pattern transfer, underlying CdTe films were etched (after development of the resist) in an electron cyclotron resonance (ECR) plasma, where etch selectivities of approximately 8:1 have been achieved. The significance of this work is the demonstration of laser-induced poly-Si as an etching mask for vacuum-compatible photolithography.     

Selective CdTe Nanoheteroepitaxial Growth on Si(100) Substrates Using the Close-Spaced Sublimation Technique Without the Use of a Mask

The development of HgCdTe detectors requires high sensitivity, small pixel size, low defect density, long-term thermal-cycling reliability, and large-area substrates. CdTe bulk substrates were initially used for epitaxial growth of HgCdTe films. However, CdTe has a lattice mismatch with long-wavelength infrared (LWIR) and middle-wavelength infrared (MWIR) HgCdTe that results in detrimental dislocation densities above mid-10⁶ cm^?2. This work explores the use of CdTe/Si as a possible substrate for HgCdTe detectors. Although there is a 19% lattice mismatch between CdTe and Si, the nanoheteroepitaxy (NHE) technique makes it possible to grow CdTe on Si substrates with fewer defects at the CdTe/Si interface. In this work, Si(100) was patterned using photolithography and dry etching to create 500-nm to 1-μm pillars. CdTe was selectively deposited on the pillar surfaces using the close-spaced sublimation (CSS) technique. Scanning electron microscopy (SEM) was used to characterize the CdTe selective growth and grain morphology, and transmission electron microscopy (TEM) was used to analyze the structure and quality of the grains. CdTe selectivity was achieved for most of the substrate and source temperatures used in this study. The ability to selectively deposit CdTe on patterned Si(100) substrates without the use of a mask or seed layer has not been observed before using the CSS technique. The results from this study confirm that CSS has the potential to be an effective and low-cost technique for selective nanoheteroepitaxial growth of CdTe films on Si(100) substrates for infrared detector applications.     

New wet etching solution molar ratio for processing T2SLs InAs/GaSb nBn MWIR infrared detectors grown on GaSb substrates

Mid-wave infrared (MWIR) technology is dominated by HgCdTe. However, in terms of performance, InAs/GaSb type-II superlattice (T2SL) has shown the theoretical potential to compete with HgCdTe. T2SLs InAs/GaSb technology is under development, where proper detector’s architecture formation must be considered as one of the most important steps of the fabrication process. The paper presents experimental results related to chemical etching of the T2SLs InAs/GaSb with bulk AlGaSb barriers, mesa type nBn MWIR detectors. Although, we attempted to transfer HgCdTe etching solutions: Br₂+C₂H₆O₂ into T2SLs InAs/GaSb technology, H₃PO₄+C₂H₈O₇+H₂O₂+H₂O (molar ratio: 1:1:4:16) at temperature ~21 °C was estimated to have optimal parameters in terms of the mesa profile and current–voltage characteristics. Repeatability of the mesa profiles and surface uniformity was reached. Overetching close to the mesa sidewalls was not observed.     

An a-Si:H vacuum-compatible photoresist process for fabricating device structures in HgCdTe

A process for transferring patterns into HgCdTe epilayers using a hydrogenated amorphous silicon (a-Si:H) photomask has been demonstrated. a-Si:H films were grown using plasma enhanced chemical vapor deposition (PECVD). A latent image of a projected mask pattern was created at the a-Si:H surface by ultraviolet enhanced oxidation in the load lock of the PECVD vacuum chamber. This image was transformed into a mask by hydrogen plasma removal of the unexposed areas. A hydrogen plasma etch selectivity value greater than 500:1 for oxide and a-Si:H allows patterns as thick as 700 nm to be generated. a-Si:H masks were used to create arrays of mesas in planar HgCdTe epilayers by etching in an electron cyclotron resonance (ECR) plasma reactor. Etch selectivity between a-Si:H and HgCdTe during an ECR hydrogen plasma etch was measured to be greater than 18:1. R_oA values > 10³ were obtained for mid-wavelength infrared diodes made from HgCdTe heterojunctions using a-Si:H masks.     

Inductively coupled plasma etching for large format HgCdTe focal plane array fabrication

Inductively coupled plasma (ICP) using hydrogen-based gas chemistry has been developed to meet requirements for deep HgCdTe mesa etching and shallow CdTe passivation etching in large format HgCdTe infrared focal plane array (FPA) fabrication. Large format 2048×2048, 20-μm unit-cell short wavelength infrared (SWIR) and 2560×512, 25-μm unit-cell midwavelength infrared (MWIR) double-layer heterojunction (DLHJ) p-on-n HgCdTe FPAs fabricated using ICP processing exhibit >99% pixel operability. The HgCdTe FPAs are grown by molecular beam epitaxy (MBE) on Si substrates with suitable buffer layers. Midwavelength infrared detectors fabricated from 4-in. MBE-grown HgCdTe/Si substrates using ICP for mesa delineation and CdTe passivation etching demonstrate measured spectral characteristics, RoA product, and quantum efficiency comparable to detectors fabricated using wet chemical processes. Mechanical samples prepared to examine physical characteristics of ICP reveal plasma with high energy and low ion angle distribution, which is necessary for fine definition, high-aspect ratio mesa etching with accurate replication of photolithographic mask dimensions.     

A large-scale parametric study of InP deposition on patterned substrates

Selective Area Epitaxy (SAE) is the process of locally depositing a semiconductor film on a substrate which has been patterned with an inert masking material such as SiO₂. During deposition by metalorganic chemical vapor deposition (MOCVD), the build up of precursors over the SiO₂ mask causes material to diffuse into the open areas leading to a growth rate increase. SAE is an important technique for electronic and photonic device fabrication, and for the monolithic integration of these devices. The present work is a single comprehensive study, which reports on the impact of all major MOCVD parameters to SAE indium phosphide films. The parameters include pressure, V/III pressure ratio, growth rate, temperature and mask geometry.     

Laser micromachining of SrTiO3 single crystal

Laser micromachining of piezoelectric materials has many advantages over other etching techniques for the fabrication of ultrasound transducer linear arrays for medical imaging. It can achieve high aspect ratios and high etch rates without the use of complicated photolithography techniques. We have investigated a laser projection etch technique to make linear arrays in single crystal (0 0 1) SrTiO₃ substrates as a model of epitaxial piezoelectric thick film heterostructure. Feature sizes of 17.5 μm were obtained with depth to width aspect ratios of 4:1. The effect of laser fluence on etching was studied and it was found that straighter sidewalls and flatter trench floors were achieved as laser fluence increases. On the other hand, higher laser fluence caused increase in heat affected zone by post-pulse plasma and made the top surfaces rougher because of the accumulation of evaporated materials. Clean top surfaces of the features were achieved by deposition and subsequent lift off of a YBa₂Cu₃O₇ sacrificial layer. In addition, the phases of recast layers on the sidewalls were characterized by four-circle X-ray diffraction with 2-D area detector before and after removed with a wet chemical etch solution. It was found that the use of the wet etchant could remove the thin polycrystalline recast layers.     

Iron nitride mask and reactive ion etching of GaN films

One of the major GaN processing challenges is useful pattern transfer. Serious photoresist mask erosion and hardening are often observed in reactive ion etching of GaN. Fine pattern transfer to GaN films using photoresist masks and complete removal of remaining photoresist after etching are very difficult. By replacing the etch mask from conventional photoresist to a sputtered iron nitride (Fe-8% N) film, which is easily patterned by wet chemical etching and is very resistive to Cl based plasmas, GaN films can be finely patterned with vertical etched sidewalls. Successful pattern transfer is realized by reactive ion etching using Cl (H) containing plasmas. CHF₃/Ar, C₂ClF₅/Ar, C₂ClF₅/Ar/O₂, SiCl₄, and CHCl₃ plasmas were used to etch GaN. The GaN etch rate is dependent on the crystalline quality of GaN. Higher crystalline quality GaN films exhibit slower etch rates than GaN films with higher dislocation and stacking fault density.     

第三代红外焦平面基础技术的研究进展

叙述了围绕第三代红外焦平面的需求所进行的HgCdTe分子束外延以及台面结芯片技术研究的一些成果。对GaAs、Si基大面积异质外延、p型掺杂以及台面刻蚀等主要难点问题进行了阐述。研究表明,7.6 cm(3 in)材料的组分均匀性良好,晶格失配引发的孪晶缺陷可以通过合适的低温成核方法得到有效抑制。在GaAs和Si衬底上外延的HgCdTe材料的(422)X射线衍射半峰宽的典型值为55″~75″。对ICP技术刻蚀HgCdTe的表面形貌、刻蚀速率、反应微观机理、负载效应和刻蚀延迟效应以及刻蚀损伤进行了研究,得到了高选择比的掩模技术和表面光亮、各向异性较好的刻蚀形貌。采用HgCdTe多层材料试制了长波n?蛳on?蛳p以及p?蛳on?蛳n型掺杂异质结器件以及双色红外短波/中波焦平面探测器,取得了一些初步结果。     

Study of the pixel-pitch reduction for HgCdTe infrared dual-band detectors

The third generation of HgCdTe infrared-detector focal-plane arrays (FPAs) should be able to detect simultaneously in two spectral bands. The feasibility of this type of dual-band detectors has already been shown in our laboratory with a pixel size of 50 μm in the 3–5-μm wavelength range. To improve the detector resolution, it is necessary to decrease the pixel pitch. Dry etching is a key process technology to fulfill this goal because of the high aspect-ratio structures needed (typically 10–15-μm deep and 2–5-μm wide trenches). In this paper, we present results of a parametric study on HgCdTe dry etching, as well as results obtained on detector arrays made with the dry-etching technique. The etching study has been done in a microwave plasma reactor with the aim of controlling the surface roughness, the etch rate, and the slope of the trench side. We show how these parameters are influenced by the reactive gas-mixture composition (based on CH₄, H₂, and Ar) and the substrate self-bias. We show how polymer film deposition can prevent etching from occurring but can improve anisotropy. We show some examples of results obtained when manufacturing the trenches that separate the pixels, keeping a high fill factor, and anisotropic etching. We also show results of the material surface characterizations done with scanning electron microscopy (SEM) and Hall effect measurements. These studies allow us to evaluate and compare the damages done to the HgCdTe surface with different etching conditions. Our best process allows us to make a light electrical damage, confined to less than a micron deep in the material. Using the dry-etching process, we have developed detector arrays fabricated with a pixel pitch as low as 30 μm. We finally present the results of the first electrical characterizations made on these arrays, showing promising results for the development of high-resolution dual-band detectors.     

大面积非光刻纳米电极间隙的制备

A lithography-independent and wafer scale method to fabricate a metal nanogap structure is demonstrated. Polysilicon was first dry etched using photoresist （PR） as the etch mask patterned by photolithography. Then, by depositing conformal SiO2 on the polysilicon pattern, etching back SiO2 anisotropically in the perpendicular direction and removing the polysilicon with KOH, a sacrificial SiO2 spacer was obtained. Finally, after metal evaporation and lifting-off of the SiO2 spacer, an 82 nm metal-gap structure was achieved. The size of the nanogap is not determined by the photolithography, but by the thickness of the SiO2. The method reported in this paper is compatible with modern semiconductor technology and can be used in mass production.     

Fabrication and characterization of two-color midwavelength/long wavelength HgCdTe infrared detectors

High-performance 20-μm unit-cell two-color detectors using an n-p⁺-n HgCdTe triple-layer heterojunction (TLHJ) device architecture grown by molecular beam epitaxy (MBE) on (211)-oriented CdZnTe substrates with midwavelength (MW) infrared and long wavelength (LW) infrared spectral bands have been demonstrated. Detectors with nominal MW and LW cut-off wavelengths of 5.5 μm and 10.5 μm, respectively, exhibit 78 K LW performance with >70 % quantum efficiency, reverse bias dark currents below 300 pA, and RA products (zero field of view, 150-mV bias) in excess of 1×10³ Ωcm². Temperature-dependent current-voltage (I–V) detector measurements show diffusion-limited LW dark current performance extending to temperatures below 70 K with good operating bias stability (150 mV ± 50 mV). These results reflect the successful implementation of MBE-grown TLHJ detector designs and the introduction of advanced photolithography techniques with inductively coupled plasma (ICP) etching to achieve high aspect ratio mesa delineation of individual detector elements with benefits to detector performance. These detector improvements complement the development of high operability large format 640×480 and 1280×720 two-color HgCdTe infrared focal plane arrays (FPAs) to support third generation forward looking infrared (FLIR) systems.     

A dry-patterned Cu(Mg) alloy film as a gate electrode in a thin-film transistor liquid crystal display

The annealing of a Cu(4.5at.%Mg)/SiO₂/Si structure in ambient O₂ at 10 mtorr and 300–500°C allows for the out-diffusion of the Mg to the Cu surface, forming a thin MgO (15 nm) layer on the surface. The surface MgO layer was patterned and successfully served as a hard mask for the subsequent dry etching of the underlying Mg-depleted Cu films using an O₂ plasma and hexafluoroacetylacetone (H(hfac)) chemistry. The resultant MgO/Cu structure, with a taper slope of about 30°, shows the feasibility of dry etching of Cu(Mg) alloy films using a surface MgO mask scheme. A dry-etched Cu(4.5at.%Mg) gate a-Si:H thin-film transistor (TFT) has a field-effect mobility of 0.86 cm²/Vs, a subthreshold swing of 1.08 V/dec, and a threshold voltage of 5.7 V. A novel process for the dry etching of Cu(Mg) alloy films that eliminates the use of a hard mask, such as Ti, and results in a reduction in the process steps is reported for the first time in this work.     

Electrical Characteristics of PEDOT:PSS Organic Contacts to HgCdTe

The electrical characteristics of organic (3,4-polyethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS) contacts to HgCdTe are studied as a potential alternative to metal/HgCdTe contacts. The use of organic PEDOT:PSS contacts offers the potential for an improved contact technology for HgCdTe IR detector arrays. In this work, PEDOT:PSS contacts are deposited on n-type and p-type HgCdTe epilayers by spin coating and patterned using a metal mask. Current-voltage (I-V) characteristics are measured on these contacts, showing nearly ohmic behavior. The temperature dependence of I-V characteristics (T = 40–300 K) shows increased resistance for decreasing temperature, consistent with the temperature dependence of HgCdTe resistivity, suggesting that the I-V characteristics are primarily dominated by the HgCdTe material.     

Heteroepitaxy of HgCdTe(112) infrared detector structures on Si(112) substrates by molecular-beam epitaxy

High-quality, single-crystal epitaxial films of CdTe(112)B and HgCdTe(112)B have been grown directly on Si(112) substrates without the need for GaAs interfacial layers. The CdTe and HgCdTe films have been characterized with optical microscopy, x-ray diffraction, wet chemical defect etching, and secondary ion mass spectrometry. HgCdTe/Si infrared detectors have also been fabricated and tested. The CdTe(112)B films are highly specular, twin-free, and have x-ray rocking curves as narrow as 72 arc-sec and near-surface etch pit density (EPD) of 2 × 10⁶ cm⁻² for 8 μm thick films. HgCdTe(112)B films deposited on Si substrates have x-ray rocking curve FWHM as low as 76 arc-sec and EPD of 3-22 × 10⁶ cm⁻². These MBE-grown epitaxial structures have been used to fabricate the first high-performance HgCdTe IR detectors grown directly on Si without use of an intermediate GaAs buffer layer. HgCdTe/Si infrared detectors have been fabricated with 40% quantum efficiency and R₀A = 1.64 × 10⁴ Ωm₂ (0 FOV) for devices with 7.8 μm cutoff wavelength at 78Kto demonstrate the capability of MBE for growth of large-area HgCdTe arrays on Si.     

HgCdTe on Si: Present status and novel buffer layer concepts

We discuss buffer-layer concepts for the synthesis of low defect-density HgCdTe epilayers on Si for both hybrid and monolithically integrated, infrared focal-plane arrays (IRFPAa). The primary technical problems to overcome include the 19% lattice-parameter mismatch between HgCdTe and Si, and the (211)B surface orientation required for molecular-beam epitaxy (MBE), the growth technique of choice for HgCdTe. We provide a general overview of IRFPAs, motivations for realizing HgCdTe on Si, the current state-of-the-art parameters as a baseline, and three novel buffer-layer concepts and technologies based on (1) obedient GeSi films on SiO₂, (2) wafer bonding, and (3) chalcogenides.