快速收敛的EG-LDPC译码算法设计实现

欧式几何构造的LDPC码属于不可分层的LDPC码,无法采用TDMP算法译码结构,针对该问题设计实现了一种新型分层译码器。在Xilinx V5 FPGA上实现了码长为1023、码率为0.781 EG-LDPC 码的译码器设计。仿真验证表明：理论上该方法与优化的规范化最小和译码算法相比,迭代次数减少一倍,存储资源消耗得到降低,而误码性能几乎相同。FPGA实现上,译码输出与MATLAB定点仿真给出的结果相同,误码性能由于量化和限幅处理与理论值相比约有0.3dB的损失。在时钟频率为50MHz串行处理各分层时,吞吐量为49.7Mbps。     

800Mbps准循环LDPC码译码器的FPGA实现

本文提出了一种适用于准循环低密度校验码的低复杂度的高并行度译码器架构。通常准循环低密度校验码不适于设计有效的高并行度高吞吐量译码器。我们通过利用准循环低密度校验码的奇偶校验矩阵的结构特点,将其转化为块准循环结构,从而能够并行化处理译码算法的行与列操作。使用这个架构,我们在Xilinx Virtex-5 LX330 FPGA上实现了(8176,7154)有限几何LDPC码的译码器,在15次迭代的条件下其译码吞吐量达到800Mbps。      

CCSDS标准LDPC部分并行译码器实现

针对CCSDS标准中近地通信的LDPC码,为了提高准循环低密度奇偶校验（QC-LDPC）译码器的吞吐率和资源利用率,设计实现了一种低复杂度高速并行译码器。译码器整体采用流水线结构,通过改进校验节点与变量节点的更新方式,在不增加运算复杂度的情况下使信息处理所消耗的时间更短,压缩单次迭代所需时间,提高了译码器的吞吐量。以现场可编程门阵列（FPGA）作为实现平台,仿真并实现了基于归一化最小和算法的（8176,7154） LDPC译码器。结果表明,当译码器工作频率为200 MHz、迭代次数为10次的情况下,译码吞吐量可达到160 Mbit/s,满足大多数场景的应用需求。     

基于FPGA的不可分层LDPC码译码器

针对不可分层LDPC码无法采用分层译码算法的问题,设计了一种新型的LDPC码分层译码器。与传统分层译码器的结构不同,新结构在各层间进行并行更新,各层内进行串行更新。通过保证在不同分层的同一变量节点不同时进行更新,达到分层译码算法分层递进更新的目标。选用Altera公司的CycloneⅢ系列EP3C120器件,实现码率3/4,码长8 192的(3,12)规则不可分层QC-LDPC码译码器的布局布线,在最大迭代次数为5次时,最高时钟频率可以达到45.44 MHz,吞吐量可以达到47.6 Mbps。     

RS码与LDPC码的联合迭代译码

针对RS码与LDPC码的串行级联结构,提出了一种基于自适应置信传播(ABP)的联合迭代译码方法.译码时,LDPC码置信传播译码器输出的软信息作为RS码ABP译码器的输入;经过一定迭代译码后,RS码译码器输出的软信息又作为LDPC译码器的输入.软输入软输出的RS译码器与LDPC译码器之间经过多次信息传递,译码性能有很大提高.码长中等的LDPC码采用这种级联方案,可以有效克服短环的影响,消除错误平层.仿真结果显示:AWGN信道下这种基于ABP的RS码与LDPC码的联合迭代译码方案可以获得约0.8 dB的增益.     

无短环不规则QC_LDPC码的快速编码及联合译码

基于不规则部分并行结构设计了一种高吞吐量,低复杂度,码长码率可变且去除四环的低密度奇偶校验LDPC码及其译码结构实现方案,该编码结构可针对不同码长的不规则部分并行结构LDPC码进行扩展,译码器采用缩放最小和定点(Sum-Min)算法实现译码,中间信息节点存储器地址采用格雷码编码,降低动态功耗;采用Xilinx公司的Virtex-5XC5Vt X150T-ff1156FPGA芯片设计了一款码长1 270,码率1 2的不规则部分并行LDPC码的编码器和译码器。综合结果表明:该编码器信息吞吐量为2.52 Gb/s,译码器在10次迭代的情况下信息吞吐率达到44 Mb/s。     

一种基于ASIP结构的LDPC译码器芯片设计

针对IEEE 802.11n标准中LDPC码多码率、多码长的特点,提出了一种基于ASIP架构的LDPC译码器设计方案。该译码器采用优化的分层译码算法、11级流水线技术以及基于ASIP结构的微指令技术,实现了4种不同码率、3种不同码长的LDPC译码功能。采用TSMC 0.18 μm CMOS工艺进行物理实现,该译码器芯片面积为3.65 mm²。测试结果表明,该设计满足IEEE 802.11n标准的译码要求。     

一种QC_LDPC码译码器的设计

根据BP译码算法,设计了一种高速部分并行QC_LDPC码译码器结构,该结构适用于所有其校验矩阵具有准循环特性的LDPC码.针对传统BP译码器的结构复杂度高,系统运行频率低和吞吐率小等特点,本设计将BP译码算法中大量的复杂函数运算通过查找表的方法来实现;校验节点和变量节点的处理均采用5级流水线的方式;采用提前终止迭代译码策略.本设计能有效地减少译码器硬件实现复杂度,同时提高系统运行地频率和数据吞吐率.     

CCSDS系统中LDPC译码器的实现

针对CCSDS系统中低密度奇偶校验码(LDPC),提出了一种低复杂度高速并行译码器实现方法。该方法利用LDPC码校验矩阵的循环结构特性,在传统的和积译码算法(SPA)上做了改进,使得在迭代次数为8的情况下,译码性能与理论值基本一致。     

基于FPGA的LDPC码编译码器联合设计

该文通过对低密度校验(LDPC)码的编译码过程进行分析,提出了一种基于FPGA的LDPC码编译码器联合设计方法,该方法使编码器和译码器共用同一校验计算电路和复用相同的RAM存储块,有效减少了硬件资源的消耗量。该方法适合于采用校验矩阵进行编码和译码的情况,不仅适用于全并行的编译码器结构,同时也适用于目前广泛采用的部分并行结构,且能够使用和积、最小和等多种译码算法。采用该方法对两组不同的LDPC码进行部分并行结构的编译码器联合设计,在Xilinx XC4VLX80 FPGA上的实现结果表明,设计得到的编码器和译码器可并行工作,且仅占用略多于单个译码器的硬件资源,提出的设计方法能够在不降低吞吐量的同时有效减少系统对硬件资源的需求。     

IEEE802.16e标准LDPC译码器设计与实现

LDPC码自在上个世纪90年代被重新发现以来,以其接近香农极限的差错控制性能,以及译码复杂度低、吞吐率高的优点引起了人们的关注,成为继Turbo码之后信道编码界的又一研究热点。利用FPGA设计并实现了一种基于IEEE802.16e标准的LDPC码译码器。该译码器采用偏移最小和（Offset Min-Sum）算法,其偏移因子β取值为0.125,具有接近置信传播（Belief Propagation）算法浮点的性能。译码器在结构上采用了部分并行结构,可以灵活支持标准中定义的所有码率和码长的LDPC码的译码。此外,该译码器还支持对连续输入的数据块进行处理,并具有动态停止迭代功能。硬件综合结果表明,该译码器工作频率为150MHz时,固定15次迭代,最低可达到95Mb/s的译码吞吐率,完全满足802.16e标准的要求。     

Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes

Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE.     

一种准循环LDPC解码器的设计与实现

面向准循环LDPC码的硬件实现,定点分析了各种解码算法的解码性能,偏移量最小和(OMS)算法具备较高解码性能和实现复杂度低的特点.提出一种基于部分并行方式的准循环LDPC解码器结构,在FPGA上利用该结构成功实现了WiMAX标准中的LDPC解码器.FPGA验证结果表明,采用该结构的解码器性能优良,实现复杂度低,数据吞吐率高.     

5G LDPC码译码器实现

该文介绍了5G标准中LDPC码的特点,比较分析了各种译码算法的性能,提出了译码器实现的总体架构：将译码器分为高速译码器和低信噪比译码器。高速译码器适用于码率高、吞吐率要求高的情形,为译码器的主体;低信噪比译码器主要针对低码率、低信噪比下的高性能译码,处理一些极限情形下的通信,对吞吐率要求不高。分别对高速译码器和低信噪比译码器进行了设计实践,给出了FPGA综合结果和吞吐率分析结果。     

5G LDPC码译码器实现

该文介绍了5G标准中LDPC码的特点,比较分析了各种译码算法的性能,提出了译码器实现的总体架构:将译码器分为高速译码器和低信噪比译码器.高速译码器适用于码率高、吞吐率要求高的情形,为译码器的主体;低信噪比译码器主要针对低码率、低信噪比下的高性能译码,处理一些极限情形下的通信,对吞吐率要求不高.分别对高速译码器和低信噪比...     

WiMAX中多码率LDPC解码器的设计与实现

针对WiMAX中多码率LDPC码,提出一种多码率LDPC解码器结构,并且在FPGA上实现了该解码器.实验结果表明:该解码器完全可以满足IEEE802.16e标准中多码率的实现要求,而且具有高吞吐率、高性能的特点.     

Fast-Converging and Low-Power LDPC Decoding: Algorithm,Architecture, and VLSI Implementation

Low-latency and energy-efficient multi-Gbps LDPC decoding requires fast-converging iterative schedules. Hardware decoder architectures based on such schedules can achieve high throughput at low clock speeds, resulting in reduced power consumption and relaxed timing closure requirements for physical VLSI design. In this work, a fast column message-passing (FCMP) schedule for decoding LDPC codes is presented and investigated. FCMP converges in half the number of iterations compared to existing serial decoding schedules, has a significantly lower computational complexity than residual-belief-propagation (RBP)-based schedules, and consumes less power compared to state-of-the-art schedules. An FCMP decoder architecture supporting IEEE 802.11ad (WiGig) LDPC codes is presented. The decoder is fully pipelined to decode two frames with no idle cycles. The architecture is synthesized using the TSMC 40 nm and 65 nm CMOS technology nodes, and operates at a clock-frequency of 200 MHz. The decoder achieves a throughput of 8.4 Gbps, and it consumes 72 mW of power when synthesized using the 40 nm technology node. This results in an energy efficiency of 8.6 pJ/bit, which is the best-reported energy-efficiency in the literature for a WiGig LDPC decoder.

     

Loosely coupled memory-based decoding architecture for low density parity check codes

Parallel decoding is required for low density parity check (LDPC) codes to achieve high decoding throughput, but it suffers from a large set of registers and complex interconnections due to randomly located 1's in the sparse parity check matrix. This paper proposes a new LDPC decoding architecture to reduce registers and alleviate complex interconnections. To reduce the number of messages to be exchanged among processing units (PUs), two data flows that can be loosely coupled are developed by allowing duplicated operations. In addition, intermediate values are grouped and stored into local storages each of which is accessed by only one PU. In order to save area, local storages are implemented using memories instead of registers. A partially parallel architecture is proposed to promote the memory usage and an efficient algorithm that schedules the processing order of the partially parallel architecture is also proposed to reduce the overall processing time by overlapping operations. To verify the proposed architecture, a 1024 bit rate-1/2 LDPC decoder is implemented using a 0.18-/spl mu/m CMOS process. The decoder runs correctly at the frequency of 200 MHz, which enables almost 1 Gbps decoding throughput. Since the proposed decoder occupies an area of 10.08 mm/sup 2/, it is less than one fifth of area compared to the previous architecture.     

FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.