Temperature Measurement of Semitransparent Silicon Wafers Based Upon Absorption Edge Wavelength Shift

The temperature dependence of silicon wafer transmittance is well understood, and is caused by various absorption mechanisms over a wide spectral range. As the wavelength increases, the photon energy decreases until it becomes lower than the minimum energy gap in the silicon band structure. At this point, which is often referred to as the absorption edge wavelength, there is a rapid drop in absorption. The absorption edge shifts to a longer wavelength with increasing temperature, because the bandgap narrows with increasing temperature. Experiments were carried out with varying wavelength (900 nm to 1700 nm), polarization (p- and s-polarized), and direction (from normal to 80°), using specimens with different resistivities (0.01 Ω · cm to 2000 Ω · cm). A characteristic curve relating the absorption edge wavelength and temperature was obtained for all of the silicon wafers, despite their differing resistivity. This method enables in situ temperature measurements of silicon wafers from room temperature to 900 K, using wavelengths to which the wafer is semitransparent. In this article, an experimental apparatus and measurement results are described in detail, and several remaining problems are discussed.     

Deposition of BaTiO3 thin films by plasma MOCVD

Barium titanium trioxide (BaTiO₃) thin films were deposited on fused silica or silicon wafer substrate from barium dipivaloylmethanate (II) (Ba(dpm)₂) and titanium tetraisopropoxide (IV) (TTIP) used as precursors in an oxygen microwave plasma. The substrates were dielectrically heated and the substrate temperatures were around 900 K during the film deposition. The deposition was performed for 15 min and the deposits were identified as BaTiO₃ by means of X-ray diffraction, X-ray photoelectron spectroscopy, infrared spectroscopy, and ellipsometry. Oxygen and barium atoms and TiO and CO molecules were identified in the plasma. These species would produce higher deposition rates at lower substrate temperatures than those did in the usual thermal metalorganic chemical vapor deposition (MOCVD). The dielectric constant of the BaTiO₃ thin film that was directly deposited on the silicon wafer substrate was as low as 10¹ order of magnitude. Because the deposit reacted with the substrate and an interdiffusional layer was formed, the platinum layer was coated on the silicon wafer substrate in order to prevent the formation of an interdiffusional layer. The dielectric constant then increased to 10³ order of magnitude.     

Rapid-Response Hybrid-Type Surface-Temperature Sensor

A hybrid-type surface-temperature sensor that combines the advantages of contact and non-contact sensing methods has been developed and that offers a way to overcome the weak points of both methods. The hybrid-type surface-temperature sensor is composed of two main components: a metal film that makes contact with the object and an optical sensor that is used to detect the radiance of the rear surface of the metal film. Temperature measurement using this thermometer is possible with an uncertainty of 0.5 K after compensating for systematic errors in the temperature range from 900 to 1,000 K. The response time of our previous hybrid-type sensor is, however, as long as several tens of seconds because the measurement must be carried out under thermally steady-state conditions. In order to overcome this problem, a newly devised rapid-response hybrid-type surface-temperature sensor was developed and that can measure the temperature of an object within 1 s by utilizing its transient heat transfer response. Currently, the temperature of a silicon wafer can be measured with an uncertainty of 1.0 K in the temperature range from 900 to 1,000 K. This sensor is expected to provide a useful means to calibrate in situ temperature measurements in various processes, especially in the semiconductor industry. This article introduces the basic concept and presents experimental results and discussions.     

Growth of Fe on Si (100) at room temperature and formation of iron silicide

Low-energy electron diffraction (LEED), Auger electron spectroscopy and X-ray photoelectron spectroscopy (XPS) investigations of both the growth of an iron film on silicon (100) at room temperature and the subsequent formation of iron silicide are the subjects of this paper. An in-situ cleaned silicon (100) wafer without carbon or oxygen contamination exhibiting the known 2 × 1 reconstruction in the LEED pattern served as the substrate. Iron was deposited on this reconstructed surface at 300 K. The comparison of theoretical calculations based on three growth mechanisms with XPS data obtained with take-off angles of 0° and 50° clearly demonstrates a layer-by-layer growth of the iron film on silicon (100). At 300 K no formation of iron silicide was observed, although an interaction between iron and silicon could be detected at the interface. The formation of iron silicide was observed at annealing temperatures of 630–730 K. Quantitative XPS analysis yields the presence of FeSi₂, when the thickness is large enough. Neither the iron film on silicon nor the silicide shows any LEED pattern.     

一种新型腐蚀剂——醋酸钠溶液对单晶硅太阳电池表面织构化的作用

对晶向为(100)的p型单晶硅片进行表面刻蚀,制作减反射绒面。选用了一种新型的腐蚀剂,即醋酸钠(CH3COONa)溶液,用来腐蚀单晶硅太阳电池。通过分别改变醋酸钠溶液的浓度、温度以及腐蚀时间对硅片表面进行腐蚀发现,经醋酸钠溶液腐蚀后在硅片表面形成腐蚀坑大小适中、分布均匀的绒面结构。在醋酸钠溶液的质量分数为20%、温度为95℃、时间为40min的条件下腐蚀单晶硅片,在波长为700～1000nm之间获得较低的平均表面反射率,且最佳平均反射率为12.14%。从实验结果和成本因素考虑,这种腐蚀剂的成本很低,不易污染环境且重复性好,有利于大规模工业化制绒。     

材料特性对亲水性固结磨料研磨垫加工性能的影响

为研究材料特性对亲水性固结磨料研磨垫的加工性能影响,本文研究了K9玻璃和硅片两种材料在不同加工顺序下研磨过程中的声发射信号和摩擦系数特征,采用扫描电镜分析磨屑的尺寸与形态.结果表明:不同加工顺序下工件的材料去除速率差别很大.与直接研磨硅片相比,先研磨K9玻璃再研磨硅片,硅片的材料去除速率大幅下降;相反,先研磨硅片再研磨K9玻璃,与直接研磨K9玻璃相比,K9玻璃的材料去除速率变化不大.无论采用哪种加工顺序,后研磨的工件表面粗糙度均比直接研磨的同种工件要大.扫描电镜的分析表明,硅片的磨屑尺寸集中在600 nm~1.5μm,磨屑大部分都棱角完整;而K9玻璃的磨屑尺寸集中在300 nm~500 nm左右,无明显棱角.硅片磨屑较大的尺寸与完整的棱角促进了研磨垫的自修正过程,所以硅片这类脆性较大的材料有利于研磨垫的自修正过程.     

Fabrication and testing of bulk micromachined silicon carbide piezoresistive pressure sensors for high temperature applications

This paper explores the development of high-temperature pressure sensors based on polycrystalline and single-crystalline 3C-SiC piezoresistors and fabricated by bulk micromachining the underlying 100-mm diameter (100) silicon substrate. In one embodiment, phosphorus-doped APCVD polycrystalline 3C-SiC (poly-SiC) was used for the piezoresistors and sensor diaphragm, with LPCVD silicon nitride employed to electrically isolate the piezoresistor from the diaphragm. These piezoresistors fabricated from poly-SiC films deposited at different temperatures and doping levels were characterized, showing -2.1 as the best gauge factor and exhibited a sensitivities up to 20.9-mV/V*psi at room temperature. In a second embodiment, epitaxially-grown unintentionally nitrogen-doped single-crystalline 3C-SiC piezoresistors were fabricated on silicon diaphragms, with thermally grown silicon dioxide employed for the piezoresistor electrical isolation from the diaphragm. The associated 3C-SiC/SiO/sub 2//Si substrate was fabricated by bonding a (100) silicon wafer carrying the 3C-SiC onto a silicon wafer with thermal oxide covering its surface. The 3C-SiC handle wafer was then etched away in KOH. The diaphragm was fabricated by time etching the silicon substrate. The sensors were tested at temperatures up to 400/spl deg/C and exhibited a sensitivity of 177.6-mV/V*psi at room temperature and 63.1-mV/V*psi at 400/spl deg/C. The estimated longitudinal gauge factor of 3C-SiC piezoresistors along the [100] direction was estimated at about -18 at room temperature and -7 at 400/spl deg/C.     

Effect of annealing temperature on ZnO:Al/p-Si heterojunctions

Al-doped, zinc oxide (ZnO:Al) films with a 1.2 at.% Al concentration were deposited on p-type silicon wafers using a sol-gel dip coating technique to produce a ZnO:Al/p-Si heterojunction. Following deposition and subsequent drying processes, the films were annealed in vacuum at five different temperatures between 550 and 900 °C for 1 h. The resistivity of the films decreased with increasing annealing temperature, and an annealing temperature of 700 °C provided controlled current flow through the ZnO:Al/p-Si heterojunction up to 20 V. The ZnO:Al film deposited on a p-type silicon wafer with 1.2 at.% Al concentration was concluded to have the potential for use in electronic devices as a diode after annealing at 700 °C.     

退火温度对硅基溅射铜膜应力的影响

采用光学相移法 ,对Si基片上Cu膜应力随退火温度的变化进行了研究。研究表明 :随退火温度的升高 ,Cu膜应力减小 ,2 0 0℃时平均应力减小为 - 0 2 6 1× 10 8Pa,且应力分布均匀 ,在选区范围内应力差仅为 2 2 4 4× 10 8Pa。同时用X射线衍射技术测量分析了Cu膜经过不同退火温度热处理后的微结构组织 ,研究了Cu膜的微结构对其应力的影响     

Bottom-gated epitaxial graphene

High-quality epitaxial graphene on silicon carbide (SiC) is today available in wafer size. Similar to exfoliated graphene, its charge carriers are governed by the Dirac-Weyl Hamiltonian and it shows excellent mobilities. For many experiments with graphene, in particular for surface science, a bottom gate is desirable. Commonly, exfoliated graphene flakes are placed on an oxidized silicon wafer that readily provides a bottom gate. However, this cannot be applied to epitaxial graphene as the SiC provides the source material out of which graphene grows. Here, we present a reliable scheme for the fabrication of bottom-gated epitaxial graphene devices, which is based on nitrogen (N) implantation into a SiC wafer and subsequent graphene growth. We demonstrate working devices in a broad temperature range from 6 to 300 K. Two gating regimes can be addressed, which opens a wide engineering space for tailored devices by controlling the doping of the gate structure.     

Nickel diffusion and silicide island formation on silicon (111)

Crystalline nickel disilicide islands have been observed on the Si(111) surface by atomic force microscopy (AFM). The nickel disilicide islands coalesce following a high temperature anneal (≈1260K). The islands differ from those formed at lower temperature in both shape and orientation. To explain the differences, we discuss kinetically limited growth accompanying phase and surface segregation of Ni from the bulk silicon wafer, and condensation of a Ni-rich NiSi_2−x liquid phase at the surface. Condensation from the liquid phase to NiSi₂ is concluded to be responsible for the structure of the crystallites. High temperature growth conditions lead preferentially to A-type (non-twinned) silicide structures.     

Nondestructive evaluation of large-area PZN-8%PT single crystal wafers for medical ultrasound imaging probe applications

A nondestructive quality evaluation and control procedure for large-area, (001)-cut PZN-8%PT wafers is described. The crystals were grown by the flux technique engineered to promote (001) layer growth of the crystals. The wafers were sliced parallel to the (001) layer growth plane. Curie temperature (Tc) variations, measured with matching arrays of dot electrodes (of 5.0 mm in center-to-center spacing), were found to be better than +/- 4.0 degrees C both within wafers and from wafer to wafer. After selective dicing to give final wafers of narrower Tc distributions (e.g., +/- 3.0 degrees C or better), the wafers were coated with complete electrodes and poled at room temperature at 0.7-0.9 kV/mm. Typical overall properties of the poled wafers were: K3T = 5,200 (+/- 10% from wafer to wafer), tan delta < 0.01 (all wafers), and kt = 0.55 (+/- 5%) (all percentage variations are in relative percentages). Then, the distributions of K3S, tan delta, and kt were measured by the array dot electrode technique. The variations in K3S (hence K3T) and kt within individual wafers were found to be within +/- 10% and +/- 5%, respectively. The dielectric loss values, measured at 1 kHz, were consistently low, being < 0.01 throughout the wafers. The kt values determined by the dot electrodes were found to be about 5% smaller than those obtained with the complete electrodes, which can be attributed to an increase in capacitance ratio due to the partial electroding. The k33 values, deduced using the relation K3S approximately (1 - k33(2))K3T, from the mean K3S and overall K3T values, average 0.94 (+/- 2%). The present work shows that the distribution of Tc within wafers can be used as a convenient check for the uniformity in composition and electromechanical properties of PZN-8%PT single crystal wafers. Our results show that, to control deltaK3T and deltakt within individual wafer to < or = 10% and 5%, respectively, the variation in Tc within the wafer should be kept within +/- 3.0 degrees C or better.     

Interfacial adhesion of polymeric adhesive film on different surfaces in the fabrication of polymer photonic devices

One main critical issue in the fabrication of polymer optical devices is the adhesion strength of polymeric layer to the substrate. High adhesion strength is desirable and critical in order to avoid peeling out of polymeric layer from the substrate due to stress generated during fabrication, handling and lifetime. Therefore, the aim of this study is to investigate the interfacial adhesion of polymeric adhesive film on different possible substrate surfaces such as pure silicon wafer, silica on silicon wafer, and thin metal layer (Chromium–Cr) on silicon wafer under different processing conditions. Surface morphology of the substrates before deposition was characterized by atomic force microscope (AFM). Adhesive shear button was made on those substrates by using photolithography process and the interfacial adhesion was measured by using a Dage D2400 shear tester. The effect of exposing in high temperature and typical damp heat condition on the interfacial adhesion was also studied. We found that the best adhesion performance was obtained for the case using Cr thin in all processing conditions, especially under heat treatment and damp heat test. From this study, we suggest that a thin layer of metal film on silicon wafer can be use to improve the adhesion and the reliability of the polymer photonic devices. The oxidized silica on silicon wafer is an alternative choice at the expense of reducing adhesion performance. Moreover, using silica layer has the advantage over Cr layer that one fabrication step can be reduced since the silica layer itself can effectively act as the lower cladding of the devices.     

大面积高深宽比微结构硅片的热氧化实验研究

利用大面积硅片制作X射线光栅和硅基微通道板等都涉及硅的热氧化工艺。热氧化使具有高深宽比微结构的大面积硅片产生形变,严重影响了这些器件的应用。本文以5英寸硅片为例,研究了硅基微结构在热氧化过程中的变形问题,定性分析了产生形变的力学因素,提出了减小形变的氧化方法。首先实验制作了具有高深宽比微结构的硅片,采用不同的氧化方法,比较了变形的大小。结果表明,通过控制热氧化过程中的温度来控制热膨胀系数和在热氧化过程中施加外部热塑应力等方法能够有效地减小热氧化变形量。     

水热法制备不同形貌的氧化锌纳米结构

采用水热法,用甲酰胺水溶液和锌片建立反应体系,在不同种晶层上制备出不同形貌的ZnO纳米结构,所用基底有Si片、镀有ZnO薄膜的Si片、镀有ITO薄膜的Si片、涂有ZnO粉末的Si片等,研究了不同的种晶层对ZnO纳米结构的形貌的影响。在不同温度下,分别在镀有ZnO薄膜和ITO薄膜的医用载玻片衬底上生长ZnO纳米结构,研究了温度在水热法中的作用及种晶层对纳米杆长度的影响。实验中用扫描电子显微镜（SEM）和X射线衍射仪（XRD）对纳米聚集体进行了表征。SEM表征结果表明不同种晶层上获得的ZnO纳米结构形貌差异很大;反应时间、甲酰胺水溶液浓度以及反应温度对ZnO纳米阵列形貌都有着一定的影响;在ZnO薄膜上生长的纳米杆较在ITO薄膜上生长的纳米杆长。SEM图像同时表明氧化锌纳米杆随着温度的增大,纳米杆的长度和杆径增大。X射线衍射峰在34.6℃有很强的（002）纤锌矿衍射峰,该峰表明衬底上有高度c轴取向的大面积纳米杆阵列和较好的结晶质量。     

Deformation of carbon nanotubes colliding with a silicon surface and its dependence on temperature

Using molecular dynamics simulation, we investigated the carbon nanotubes (CNTs) colliding with a silicon surface at a speed of 600 m/s, mimicking cold spray experiments of CNTs. Depending on temperature (300-900 K), the CNT is deposited on or bounces off the surface after impact on the surface. The CNT was more deformed as its temperature rose. The deformation of CNT was maximal for the collision geometry where the long axis of CNT lies parallel to the surface plane. However, its vibrational energy was maximal when the CNT collided with its long axis perpendicular to the surface.     

Atomic layer deposition of SiO2 thin films using tetrakis(ethylamino)silane and ozone

We examined the atomic layer deposition (ALD) of silicon dioxide thin films on a silicon wafer by alternating exposures to tetrakis(ethylamino)silane [Si(NHC2H5)4] and O3. The growth kinetics of silicon oxide films was examined at substrate temperatures ranging from 325 to 514 degrees C. The deposition was governed by a self-limiting surface reaction, and the growth rate at 478 degrees C was saturated at 0.17 nm/cycle for Si(NHC2H5)4 exposures of 2 x 10(6) L (1 L = 10(-6) Torr x s). The films deposited at 365-404 degrees C exhibited a higher deposition rate of 0.20-0.21 nm/cycle. However, they contained impurities, such as carbon and nitrogen, and showed poor film qualities. The concentration of impurities decreased with increasing substrate temperature. It was found that the films deposited in the high-temperature regime (478-514 degrees C) showed excellent physical and electrical properties equivalent to those of LPCVD films.     

The effect of water desorption and organosilane coupling agents on the adhesion of poly(p-xylylene) films to a silicon wafer surface

The adhesion strength of a poly(p-xylylene) (PPX) film to a silicon wafer surface deposited from the vapor was studied using a peel test method. It was found that, within the time and the temperature range studied in this work, the adhesion strength increases with the time and the temperature of the vacuum desiccation of the surface prior to the deposition of the film. This shows that the presence of water adsorbed on the surface strongly decreases the adhesion strength of the film. The effect of organosilane coupling agents on the adhesion of the film to the silicon wafer surface was studied for organosilane derivatives of different chemical compositions. It was found that the adhesion strength can be significantly improved by the presence of 3-(trimethoxysilyl)propyl methacrylate vapor before or during the poly(p-xylylene) deposition. No significant effect on PPX film adhesion was observed for other organosilanes having the propylmethacrylate group replaced by phenyl or alkyl groups. It was found that, in contrast to the other organosilanes, the recrystallization of the PPX from solution did not remove the methacrylate organosilane which remained bonded to the PPX crystals. It is suggested that chemical bonding between the methacrylic group and the PPX chain end radicals is responsible for the improved adhesion of the PPX films.     

Temperature-programmed GC using silicon microfabricated columns with integrated heaters and temperature sensors

Columns were fabricated in silicon substrates by deep reactive-ion etching. The channels were sealed with a glass wafer anodically bonded to the silicon surface. Heaters and temperature sensors were fabricated on the back side of each column chip. A microcontroller-based temperature controller was used with a PC for temperature programming. Temperature programming, with channel lengths of 3.0 and 0.25 m, is described. The 3.0-m-long channel was fabricated on a 3.2 cmx3.2 cm chip. Four columns were fabricated on a standard 4-in. silicon wafer. The 0.25-m-long channel was fabricated on a 1.1 cmx1.1 cm chip, and approximately 40 columns could be fabricated on a 4-in. wafer. All columns were coated with a nonpolar poly(dimethylsiloxanes) stationary phase. A static coating procedure was employed. The 3.0-m-long column generated about 12000 theoretical plates, and the 0.25-m-long channel generated about 1000 plates at optimal carrier gas velocity. Linear temperature ramps as high as 1000 degrees C/min when temperature programmed from 30 to 200 degrees C were obtained with the shorter column. With the 0.25-m-long column, normal alkanes from n-C5 through n-C15 were eluted in less than 12 s using a temperature ramp rate of 1000 degrees C/min. Temperature uniformity over the column chip surface was measured with infrared imaging. A variation of about 2 degrees C was obtained for the 3.0-m-long channel. Retention time reproducibility with temperature programming typically ranged from +/-0.15% to +/-1.5%. Design of the columns and the temperature controller are discussed. Performance data are presented for the different columns lengths.     

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 μm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.