与工艺、电源电压和温度无关的低功耗振荡环设计

分析了传统片外时钟和片内时钟各自的特点和应用背景,在Chartered 0.35μm CMOS工艺下实现了一个低功耗PVT(工艺、电源电压、温度无关)振荡环,对片内时钟的稳定性和功耗进行改进。该振荡环无需精准的电压源,采用了误差补偿技术,通过偏置电压和延时单元的相互补偿,使得振荡频率对于工艺、温度和电源电压均有较大的容差能力。并且由于针对延时单元补偿的方式,令周期大小易于调整。蒙特卡罗仿真显示,工艺误差引起的偏差要比补偿前的偏差减小了60%。流片测试结果表明,在工作温度变化范围0~100°C时,振荡环输出的频率偏差为±3.22%;在电源电压变化范围为2.8~3.8 V时,振荡环输出的频率偏差为±3.36%;在电源电压3.3 V的情况下,整个芯片消耗的电流为950μA。     

A high-frequency temperature-stable monolithic VCO

A new high-frequency monolithic voltage-controlled oscillator (VCO) is described that achieves /spl plusmn/60 ppm//spl deg/C temperature coefficient of frequency over 0-75/spl deg/C at center frequencies from DC to 20 MHz. The circuit also exhibits good linearity of voltage to frequency, and excellent triangle output waveform over the whole frequency range from low frequencies to 20 MHz. The circuit is fabricated using an eight mask IC process and has a die size of 65/spl times/50 mils/SUP 2/.     

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.     

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.     

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer andtemperature-compensated tunable oscillator

This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter of 3.1 ps was measured for a 1.6-GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0°C to 85°C. The circuits were fabricated on a generic 0.5-μm digital CMOS process     

A 44-/spl mu/W 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range

A microwatt frequency divider for the 2.5-GHz ISM band is proposed. This divider directly modulates the output in a ring oscillator by means of a switch and realizes low power consumption with low supply voltage and a wide locking range. It is fabricated using a five-layer-metal and 0.2-/spl mu/m-gate length CMOS process. The core size is 10.8/spl times/10.5 /spl mu/m/sup 2/, which is much smaller than that of a typical inductor-enhanced frequency divider. This divider operates with a supply voltage in the range from 1.8 to 0.7V, and attains minimum power consumption of 44 /spl mu/W, in which case the supply voltage is 0.7 V, the maximum operating frequency is 4.3 GHz, and the locking range is 2.3 GHz. A derivation of the frequency locking range of the divider is provided in the Appendix.     

A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0

A monolithic and self-referenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a system-on-chip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phase-locked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low far-from-carrier phase noise to achieve low jitter. From a 1.536 GHz temperature-compensated LC reference oscillator, coherent clock signals are derived at 96MHz for the SoC logic and 12 MHz for an on-chip full-speed USB PHY. Though self-referenced, approximately plusmn400ppm total frequency accuracy is achieved over process variations, plusmn10% variation in the USB power supply voltage and temperature variation from -10 to +85degC. Measured period and cycle-to-cycle jitter are 6.78 ps_rms and 8.96 ps_rms, respectively. Fabricated in a 0.35 mum CMOS technology, the clock generator occupies 0.22 mm² and draws 9.5 mA from a 3.3-V supply, which is derived from the 5-V USB power supply     

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.     

A temperature- and process-tolerant 64K EEPROM

A 64K EEPROM is described with emphasis on the circuit techniques used to achieve extended temperature operation. The core architecture is considered and a suitable byte layout which eliminates possible punchthrough in the memory cell is shown. A feedback-controlled substrate bias generator is described which delivers -1.0 V/spl plusmn/0.05 V and reduces significantly field transistor leakages. In addition, a /spl plusmn/1% stable voltage reference is shown to accurately control the programming voltage for the memory array to 20 V/spl plusmn/1 V over the full military temperature range (-55/spl deg/-+125/spl deg/C) and /spl plusmn/10% power-supply variation. A process-insensitive write timing pulse trimmed by E2 fuses is discussed, as is the PAGE-MODE WRITE circuitry in relation to the bitline latches.     

An accurate current source with on-chip self-calibration circuits for low-voltage current-mode differential drivers

An accurate CMOS current source for current-mode low-voltage differential transmitter drivers has been designed and fabricated. It is composed of binary weighted current mirrors with built-in self-calibration circuits. The proposed self-measurement and calibration circuits can calibrate upon the collective effects of different error contributors due to process, power supply, and temperature variations. The design has been fabricated in standard 0.35-/spl mu/m CMOS technology. Measurement results show that the differential output voltage can be self-calibrated to /spl plusmn/1% accuracy with 16% reference current variation, 60% power supply variation, or 13% load resistance variation, respectively.     

A new single-chip C/SUP 2/MOS A/D converter for microprocessor systems-Penta-Phase Integrating C/SUP 2/MOS A/D converter

A new unique conversion technique named the `Penta-Phase Integration' method, applied to a single-chip C/SUP 2/MOS 12-bit analog-to-digital converter designed for microprocessor system, is introduced and described. The newly developed device, fabricated with a standard metal gate CMOS process including an 8-channel multiplexer and TTL compatibility, has several features: unipolar- and ratiometric-conversion can be performed; conversion accuracy within /spl plusmn/0.05 percent of full scale over the -35/spl deg/C-+85/spl deg/C temperature range can be obtained; conversion time is 1.1 ms at a 20 MHz clock frequency, and the device can be operated with a single 5 V power supply and 6 mW power consumption at a 4 MHz clock frequency. The new technique essentially incorporated several methods which divide one conversion cycle into five-phases, accomplish minimization of the error caused by comparator response delay, provide several narrow flat phases to eliminate switching errors due to parasitic capacitance, and enable high clock frequency operation in digital circuits by utilizing C/SUP 2/MOS circuit technology and a synchronized configuration for counters.     

低电压环形振荡器设计

提出了一种新的两级环形振荡器结构，通过控制PMOS的衬底电压，来降低PMOS管的阈值电压，从而使新的环形振荡器可以在低电压下工作到很高的频率。仿真结果表明，在电源电压为1V，调节电压在0～1V范围内变化时，振荡器的频率为300MHz-4GHz。     

A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC

A low voltage-power, 13-bit and 16 MSPS analog-to-digital converter (ADC) was implemented in 0.25-/spl mu/m one-poly five-metal standard CMOS process with MIM capacitors. This ADC used a constant-gm switch to improve the nonlinear effect and a telescopic operational transconductance amplifier with a wide-swing biasing technique for power saving and low supply voltage operation. The converter achieved a peak SNDR of 59.2 dB with 16.384 MSPS, a low supply voltage of 1.3V, and Nyquist input frequency of 8.75 MHz. The static INL of /spl plusmn/2.0 LSB and DNL of /spl plusmn/0.5 LSB were obtained. The total power consumption of this converter was 78 mW. This chip occupied 3.4 mm /spl times/ 3.6 mm area.     

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/spl mu/m CMOS process with core area of 0.16 mm/sup 2/. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.     

Frequency-adjustable clock oscillator based on frequency-to-voltage converter

A frequency-adjustable clock oscillator based on a frequency-to-voltage converter is presented. A new architecture is employed without reference frequency input. The system model shows the conditions of system stability. A compensation circuit was used to cancel the variations of frequency over process and temperature. The range of output frequency is from 22.5-360 MHz, which is within +4.5% variation in worst cases. The circuit was designed in a 0.13 μm CMOS 3.3 V device process, occupying a chip area of about 0.05 mm². The clock oscillator can achieve 25 ps peak-to-peak jitter, 2 μs locked time and consume 5 m W at a 3.3 V supply voltage and 200 MHz output clock.     

An integrated IF amplifier

An IF amplifier that provides a temperature insensitive Q (adjustable independently of center frequency) of 50 at a center frequency of f/SUB 0/ of 1 MHz, over a 100/spl deg/C temperature range is presented. The design also features supply independent biasing, input and output buffering, a 40-dB (automatic gain control) range and a center frequency voltage gain of up to 60 dB. Results obtained from computer simulations, discrete, and integrated prototypes are compared.     

1-GHz, 200/spl deg/C, SiC MESFET Clapp oscillator

A SiC Clapp oscillator fabricated on an alumina substrate with chip capacitors and spiral inductors is designed for high-temperature operation at 1GHz. The oscillator operated from 30/spl deg/C to 200/spl deg/C with an output power of 21.8dBm at 1GHz and 200/spl deg/C. The efficiency at 200/spl deg/ C is 15%. The frequency variation over the temperature range is less than 0.5%.     

1 V CMOS current reference with 50 ppm//spl deg/C temperature coefficient

A CMOS current reference circuit is presented, which can work properly with a supply voltage higher than 1 V. By compensating the temperature performance of the resistor, this circuit gives out a current with a temperature coefficient of 50 ppm//spl deg/C over the temperature range of (0/spl deg/C, 110/spl deg/C) and a 0.5% variation for a supply voltage of 1 to 2.3 V.     

A wide-band CMOS injection-locked ring oscillator

An injection-locked ring oscillator fabricated in a 0.18-/spl mu/m CMOS process is presented for high-speed applications. By tuning the free-running frequency, the proposed circuit provides 2:1 and 4:1 frequency division over a wide input frequency range. The measured input frequency range covers 16.7-25.2 GHz and 41.2-46.9 GHz for 2:1 and 4:1 frequency division, respectively. The divider core operates at a 1.8-V supply voltage with a power consumption between 21.0 and 23.8mW for the entire frequency tuning range.     

Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.