BDD decomposition for delay oriented pass transistor logic synthesis

We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the max-flow min-cut technique to bipartition the BDD optimally under a cost function that measures the delay and area of the decomposed implementations. Experimental results obtained by running our algorithm on the set of ISCAS'85 benchmarks show a 31% improvement in delay and a 30% improvement in area, on an average, as compared to static CMOS implementations for XOR intensive circuits, while in case of arithmetic logic unit and control circuits that are NAND intensive, improvements over static CMOS are small and inconsistent.     

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment

This brief presents a logic synthesis flow that depends on the popular Synopsys Design Compiler to perform logic translation and minimization based on the standard cell library with both pass transistor logic (PTL) and CMOS logic cells. The hybrid PTL/CMOS logic synthesis can generate appropriate circuits considering various design constraints. The proposed multilevel PTL logic cells are automatically constructed from only a few basic cells. Postlayout simulations with UMC 90-nm technology are presented based on the standard cell library with pure PTL, pure CMOS, or hybrid PTL/CMOS cells. Experimental results show that, in most cases, pure PTL circuits have smaller area and power, whereas CMOS circuits, in general, have smaller delay.      

Complex 3D CMOS circuits based on a triple-decker cell

Presents circuit design for a three-dimensional (3D) CMOS integrated process. This process, with its three stacked transistor channels, leads to the very efficient basic circuits: inverter, selector, and NAND2. These elements are used to build a complete cell library with standard elements like NORs, latches, flip-flops, etc. Special macro blocks such as multipliers, SRAMs and content addressable memories (CAMs) complete the circuit library. Novel concepts and implementations of three-dimensional prefabricated semicustom arrays are introduced. These are the NAND array and the selector array, for which technology-dependent logic synthesis is investigated. Area requirements for static 3-D CMOS logic ranges from 50% down to 33% compared to two-dimensional (2-D) CMOS. These figures include the wiring and are caused by the transistor stacking and the large number of interconnection layers used in the 3D CMOS process.<>     

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

Full-swing Schottky BiCMOS/BiNMOS and the effects of operatingfrequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V_DD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits     

Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%.      

The impact of intra-die device parameter variations on path delaysand on the design for yield of low voltage digital circuits

The yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 and 0.35 μm complementary metal-oxide-semiconductor (CMOS) technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that circuits with a large number of critical paths and with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 10% is found for, for example, highly pipelined systems realized in a 0.18-μm CMOS technology     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

Asymmetric halo CMOSFET to reduce static power dissipation with improved performance

In this paper, we show the benefits of using asymmetric halo (AH, different source, and drainside halo doping concentrations) MOSFETs over conventional symmetric halo (SH) MOSFETs to reduce static leakage in sub-50-nm CMOS circuits. Device doping profiles have been optimized to achieve minimum leakage at iso on-current. Results show a 61% reduction in static leakage in AH nMOS transistor and a 90% reduction in static leakage in AH pMOS transistor because of reduced band-to-band tunneling current in the reverse biased drain-substrate junctions. In an AH CMOS inverter, static power dissipation is 19% less than in an SH CMOS inverter. Propagation delay in a three-stage ring oscillator reduces by 11% because of reduced drainside halo doping and hence reduced drain junction capacitance. Further comparisons have been made on two-input NAND and NOR CMOS logic gates.     

AND/XOR电路低功耗映射及其在最佳混合极性搜索中的应用

本文提出一种工艺无关的AND/XOR电路低功耗映射算法。该算法通过优化电路节点开关活动性实现静态MPRM电路平均功耗最小化,根据给定工艺库中的逻辑门估算MPRM电路的功耗和面积。在此基础上,结合极性转换算法获得任意极性的MPRM电路,利用遍历搜索法快速找到最佳混合极性。通过对18个MCNC和ISCAS基准电路测试表明：与FPRM电路和AND/OR电路功耗优化方案相比,混合极性搜索方案获得的AND/XOR电路功耗平均节省分别可达44.22%和60.09%,面积平均节省分别可达14.13%和32.72%。     

Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity

A low power mapping algorithm for technology independent AND/XOR circuits is proposed.In this algorithm,the average power of the static mixed-polarity Reed-Muller(MPRM) circuits is minimized by generating a two-input gates circuit to optimize the switching active of nodes,and the power and area of MPRM circuits are estimated by using gates from a given library.On the basis of obtaining an optimal power MPRM circuit,the best mixed-polarity is found by combining an exhaustive searching method with polarity conversion algorithms. Our experiments over 18 benchmark circuits show that compared to the power optimization for fixed-polarity Reed-Muller circuits and AND/OR circuits,power saving is up to 44.22%) and 60.09%,and area saving is up to 14.13%and 32.72%,respectively.     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.     

A combined gate replacement and input vector control approach for leakage current reduction

Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit's correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively.     

Wave steering to integrate logic and physical syntheses

Wave steering is a unified logic and physical synthesis scheme that algorithmically generates high-throughput circuits with fast turn-around times. Binary decision diagram (BDD)-type structures are altered to satisfy certain electrical constraints, embedded in silicon with pass transistor logic (PTL), and pipelined to very fine granularity using a novel two-phase clocking scheme. This direct PTL mapping of a logic representation provides good electrical estimations to a front-end tool like the logic synthesizer at an early phase of the design cycle. We apply our wave steering technique to high throughput computation-intensive datapath combinational circuits. We achieve an average speedup of 4.2 times compared to standard cell (SC) implementations of high performance arithmetic circuits at the cost of only about 76% average increase in area. The results look extremely encouraging; all the more so, considering that we also achieve an average reduction of 27% in latency and 15% in power compared to SC circuits.     

Gate sizing using geometric programming

A two-step transistor sizing optimization method based on geometric programming for delay/area minimization is presented. In the first step, Elmore delay is minimized using only minimum and maximum transistor size constraints. In the second step, the minimized delay found in the previous step is used as a constraint for area minimization. In this way, our method can target simultaneously both delay and area reduction. Moreover, by relaxing the minimized delay, one may further reduce area with small delay penalty. Gate sizing may be accomplished through transistor sizing tying each transistor inside a cell to a same scale factor. This reduces the solution space, but also improves runtime as less variables are necessary. To analyze this tradeoff between execution time and solution quality a comparison between gate sizing and transistor sizing is presented. In order to qualify our approach, the ISCAS??85 benchmark circuits are mapped to a 45?nm technology using a typical standard cell library. Gate sizing and transistor sizing are performed considering delay minimization. Gate sizing is able to reduce delay in 21?%, on average, for the same area and power values of the sizing provided by standard-cells library. Then, the transistor sizing is executed and delay can be reduced in 40.4?% and power consumption in 2.9?%, on average, compared to gate sizing. However, the transistor sizing takes about 23 times longer to be computed, on average, using a number of variables twice higher than gate sizing. Gate sizing optimizing area is executed considering a delay constraint. Three delay constraints are considered, the minimum delay given by delay optimization and delay 1 and 5?% higher than minimum delay. An energy/delay gain (EDG) metric is used to quantify the most efficient tradeoff. Considering the minimum delay, area (power) is reduced in 28.2?%, on average. Relaxing delay by just 1?%, area (power) is reduced in 41.7?% and the EDG metric is 41.7. Area can be reduced in 51?%, on average, relaxing delay by 5?% and EDG metric is 10.2.     

4-2 compressor of fast booth multiplier for high-speed RISC processor

A 4-2 compressor for a fast booth multiplier is designed and optimized by two circuits configurations one is constructed of different but optimized XOR circuits with 44 transistors and a total transistor size W/L of 574. The other one is made of single to dual rail transmission gates (TGs) with 56 transistors and a total transistor size W/L of 467. The maximum propagation delay, the power consumption and the chip (layout) area of the two configuration 4-2 circuits are simulated with 0.3?μm and 0.2?μm CMOS process parameters. The results show that the delay and power consumption of circuits with 0.2?μm technology are smaller than those of circuits with 0.3?μm technology. Also, 4-2 circuits are synthesized. This is supported by 0.2?μm CMOS library and design compiler (DC) software (Tools) and compared with the proposed circuits of this research, the designed TG 4-2 compressor is faster and area smaller than that of synthesized one, so the designed TG 4-2 compressors can be optimized for high speed and small chip area applications when compared with the synthesized structures.     

Exploring the design space of mixed swing quadrail for low-powerdigital circuits

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2× improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 μm process are presented to demonstrate up to 2,92× energy/operation savings for optimized mixed swing circuits compared to static CMOS