Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.     

可靠性寿命试验的动态截尾方法

为节省试验时间和资源，可靠性寿命试验通常采用定数截尾和定时截尾两种方法。但是它们有相同的不足，就是在试验结束后才进行数据分析，无法进行实时的动态控制。为解决这一问题．提出了寿命试验的动态截尾方法，利用该方法研究寿命服从指数型分布产品的可靠性试验．提出了试验动态截尾的数据处理模型及判据。该方法的思想可以推广应用于其它产品的可靠性试验与分析中。     

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%.     

第三方软件动态测试模型的研究

基于敏捷方法的测试模型大多都是发生在软件研发过程中,这种测试模型虽然客观上适用于快速迭代的软件测试过程,实际上却还是有一定的局限性,比如代码具有传递性。本文基于敏捷方法测试模型提出了一种新的动态测试模型,这种测试模型不仅节省了大量的时间以及成本,同时还为后续设备投入使用提供了有力的保证。     

Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time

The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper, a novel algorithm for the generation of SIC pairs is presented, termed Accumulator-based test generation for Robust sequential fault testing in Near-optimal time (ARN). ARN is implemented in hardware utilizing an accumulator whose inputs are driven by a barrel shifter. Since such structures are commonly found in general-purpose or specialized microprocessors or digital signal processors (DSP), the presented architecture provides a practical solution for the built-in testing of such circuits.     

A novel simulation technique for testing analog ICs

The increasing demand for reliable and high quality mixed-signal integrated circuits necessitates a defect-oriented testing methodology. Thereby fault simulation (FS) is essential for test stimuli generation and test quality assessment. Due to the high computational effort needed, analog FS is becoming a critical factor in testing mixed-signal ICs. This paper provides a new accelerated FS approach. It is based on an improved application of the Newton–Raphson method in the analysis of similarly behaving circuits. Metrics for measuring circuits' behavior similarity are presented. The new techniques are implemented in an experimental FS tool. For sample circuits, experimental results are presented and discussed.     

NoC‐Based SoC Test Scheduling Using Ant Colony Optimization

In this paper, we propose a novel ant colony optimization (ACO)‐based test scheduling method for testing network‐on‐chip (NoC)‐based systems‐on‐chip (SoCs), on the assumption that the test platform, including specific methods and configurations such as test packet routing, generation, and absorption, is installed. The ACO metaheuristic model, inspired by the ant's foraging behavior, can autonomously find better results by exploring more solution space. The proposed method efficiently combines the rectangle packing method with ACO and improves the scheduling results by dynamically choosing the test‐access‐mechanism widths for cores and changing the testing orders. The power dissipation and variable test clock mode are also considered. Experimental results using ITC’02 benchmark circuits show that the proposed algorithm can efficiently reduce overall test time. Moreover, the computation time of the algorithm is less than a few seconds in most cases.     

Improvement of integrated circuit testing reliability by using the defect based approach

The systematic decrease in the minimum feature size in VLSI circuits makes spot defects an increasingly significant cause of ICs’ faults. A testing method optimized for detecting faults of this origin has been recently developed. This method, called defect based testing (DBT), requires a lot of computational effort at the stage of testing-procedure preparation, which makes it appear less attractive than the well-known stuck-at-fault oriented testing. This paper, however, shows that a stuck-at-fault-optimized test-vector set may prove highly inefficient in detecting spot-defect-induced faults. Experiments with the C17 ISCAS-85 testability benchmark show that the risk of a spot-defect damaged circuit passing the test is dangerously high if the test set was designed with stuck-at-faults in mind. It is also shown that although spot defects may in some cases transform a combinational circuit into a sequential one, in practice this phenomenon does not require any special treatment from the test designer. Eventually, a few methods are discussed that make the DBT less time consuming.     

A test methodology for finite state machines using partial scan design

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.This research was sponsored by the Semiconductor Research Corporation, Contract 90-DP-142.     

Transparent random access memory testing for pattern sensitive faults

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.This work was supported by the NSF under Grant MIP9208487 and NATO under Grant 910411.     

A Novel RF Test Scheme Based on a DFT Method

This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides the input impedance, gain, noise figure, voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by utilizing the output DC voltages from the DFT chip. This technique can save marginally failing chips in production testing as well as in the system, hence saving a tremendous amount of revenue from unnecessary device replacements.     

A Shorter Truncated Sequential Test

This paper develops a truncated sequential test (TST) for production models that makes use of the preproduction testing and that allows unequal sample sizes from the production and the preproduction models. An example is given that compares the fixed time test (FTT) against the proposed truncated sequential test. In this example a significant reduction in testing required on the production model is achieved. Power tables for such tests are tabulated.     

A generalized two-threshold detection procedure

A modified sequential procedure for testing binary hypotheses with different means, proposed by C.C. Lee and J.B. Thomas (ibid., vol.IT-30, no.1, p.16-23, Jan. 1984), is generalized for application to the case of multiple hypotheses with different means/variances of the Gaussian distribution. The method constitutes a two-threshold test for fixed-size packages of samples with a sequential procedure of discarding the package for which no decision is reached and subsequently testing a new package. The objective is to find an optimum package size N₀ which leads to the minimum overall average sample number (ASN) for a given overall error probability. An optimization algorithm is developed to extend the application of the Lee-Thomas procedure to the M-ary case. Performance characteristics of the generalized two-threshold (GTT) test procedure are compared with those of conventional sequential as well as fixed-sample-size (FSS) methods. It is shown for the M-ary different means/variances cases that for low error rates the number of samples required by the GTT test is, on the average, approximately half that needed by a FSS test. However, it is somewhat more than the ASN obtained with a conventional sequential test. With decreasing error probabilities the GTT test performance approaches that of conventional sequential methods     

An efficient architecture for accumulator-based test generation of SIC pairs

Research conducted over the years has shown that the application of single input change (SIC) pairs of test patterns for sequential, i.e. stuck-open and delay fault testing is extremely efficient. In this paper, a novel architecture for the generation of SIC pairs is presented. The implementation of the proposed architecture is based on Ling adders that are commonly utilized in current data paths due to their high-operating speed. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.     

基于虚拟科氏力的半球谐振陀螺带宽电学自标定方法

半球谐振陀螺是一种高精度的惯性器件,在航空航天等领域有着重要的应用,但其本征带宽较低,对其力平衡控制回路及带宽测试方法要求较高。该文提出一种新型的基于虚拟科里奥利力的半球陀螺带宽电学快速测试方法,可代替角振动台等昂贵仪器对半球陀螺进行迅速自标定,从而为半球陀螺的高性能控制回路设计方法和批量化测试提供一种新的技术解决方案。首先在基础理论层面分析半球谐振陀螺动力学方程,建立起本征带宽系统模型,为虚拟电旋转的引入和自标定方法提供了理论基础。随后设计了基于虚拟科氏力的电旋转激励信号,并将其集成到陀螺接口电路系统中。最后设计了力平衡控制回路,并对该电学自标定方法进行了实验验证。实验结果表明,虚拟电旋转法能在不借助外部设备的情况下,有效准确地对半球陀螺带宽进行测试和标定,从而有效地促进高性能力平衡控制方法的开发和提高半球陀螺带宽测试效率。     

滤波器在音频DAC测试中的应用

本文给出了模拟滤波器在使用ATE（Automatic Test Equipment自动测试设备）进行高精度音频DAC（数模转换器）测试中的应用,该方法提高了测试准确度,满足了芯片量产测试的需求。论文首先介绍了DAC在ATE上的基本测试方法,然后讨论了应用滤波器的音频DAC测试方案,最后通过Matlab数学仿真和搭建电路对实际的芯片进行测试,证明了该方案的有效性。     

A wavelet‐based expert system for digital subscriber line topology identification

This work proposes a new method for automatically identifying topologies of lines with one or more sections in a telephone network. The method is based on the examination of both impulse response and time‐domain reflectometry trace of a line under test. They are analyzed using a method based on the wavelet transform that identifies and extracts features that contain information about the line topology. Those features are interpreted by an expert system composed of three sequential modules that estimate, respectively, the type of line makeup (serial or bridge tap), the lengths of the line sections, and the corresponding cable type, which are the parameters that completely identify the topology according to the assumed model. A thorough comparison with two state‐of‐the‐art methods is also presented using several twisted‐pair copper cables. The results show that the proposed method provides good accuracy with respect to topology identification at low computational cost. Copyright © 2014 John Wiley & Sons, Ltd.     

机动目标跟踪算法

针对复杂的机动目标跟踪问题,介绍了机动目标运动状态模型和固定结构的交互多模型(Interacting Multiple Model,IMM)滤波算法。在IMM基础上引入变结构思想,提出了一种基于序列似然比的变结构交互多模型(Variable Structure IMM,VSIMM)算法。通过实例仿真比较证明了该算法的有效性。     

序贯概率比检验法在导航精度试飞中的应用

以往导航精度试飞采用基于参数估计理论的误差统计法,须完成规定的试飞架次才能得出试飞结论。这里根据假设检验理论总结出序贯概率比检验法,在给定置信度和误差概率时,求出导航精度的拒绝域、接收域和观察域;当试验曲线收敛于接收域时即可提前结束试飞,达到节省架次的目的。通过应用表明该方法不但适用于导航系统,对其他系统也具参考价值。