共查询到18条相似文献,搜索用时 31 毫秒
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随着芯片集成度的发展,芯片性能越来越高,而上市时间越来越短,芯片验证在芯片设计中非常关键并贯穿于整个设计过程,验证的效率和质量直接决定着芯片的成败。提出了基于覆盖率驱动的芯片功能验证方法,定义了基于功能点覆盖率驱动的验证流程,利用PSL语言描述断言检查很有效,通过模拟工具检查断言是否成功,从而判断设计是否满足系统的功能要求。在网络接口芯片实际应用中,有效地降低了验证工作的复杂度,同时提高了验证的速度和质量。利用功能覆盖率数据判断测试激励的正确性和完整性,同时用覆盖率数据定量评价验证进程,提高了整个设计的效率。 相似文献
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随着单芯片集成度的迅速提高,硬件验证在系统设计中占有越来越重要的地位.仅由设计者完成的模块级验证已经不能够保障流片成功率,需要在验证方法学指导下采用多种先进有效的验证技术和工具,帮助设计者尽可能早地发现和修改设计缺陷.本文详细介绍了在验证方法学VMM指导下,基于IEC61375-1标准的规定,设计分层次的验证环境,对绞线式列车总线控制器进行RTL和参考模型联合仿真的功能验证技术.通过可重用VMM库和随机化函数及基于断言的验证方法,编写高效、可重用的验证平台,以提高验证效率和覆盖率.实验表明,采用覆盖率导向的验证方法可有效地减少验证工作量和验证时间,提高验证质量. 相似文献
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针对传统定向测试效率较低且容易遗漏边界条件,以及测试平台扩展性、移植性差等问题,利用SystemVerilog的面向对象特性、随机约束求解机制以及覆盖率统计机制,提出一种快速搭建覆盖率驱动的随机测试平台的方法。采用面向对象方法对指令集建模,同时定义功能覆盖点和交叉覆盖率,并对随机约束规则进行描述,利用SystemVerilog的约束求解机制在覆盖率驱动下生成大量的测试指令码。对"银河飞腾"高性能DSP芯片指令集进行验证,结果表明,与定向测试相比,随机测试的寄存器和数据通路覆盖率提高50%,操作数覆盖率提高90%以上,交叉覆盖率提高75%以上,同时功能覆盖率能在较短的时间内达到预期值,从而缩短验证周期。 相似文献
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微处理器基于功能覆盖率的伪随机验证方法 总被引:4,自引:0,他引:4
张蓓莉 《计算机与信息技术》2006,(4)
本文提出了一种基于功能覆盖率的伪随机验证方法,该方法能根据功能覆盖率的反馈自动生成测试向量进行测试,能提高验证的效率和质量,缩短设计时间,降低验证成本。 相似文献
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通过分析代码覆盖提高功能覆盖率的验证输入自动生成方法 总被引:1,自引:1,他引:0
覆盖率驱动的验证是功能验证的重要方法,但功能覆盖定义的主观性和手工调整验证输入的冗长过程都极大地影响了覆盖率驱动验证的效率.文中分析了代码行覆盖次数与功能覆盖率的内在联系,建立了基于代码行覆盖次数的概率模型,提出一种新的通过分析代码覆盖提高功能覆盖率的验证输入自动生成方法--FOCDGAG.通过代码行覆盖次数计算验证输入序列的适应度,选取对提高功能覆盖率贡献较高的输入序列,使用遗传算法自动生成新的输入序列组.实验结果表明,采用FOCDGAG时不需要功能覆盖信息,可以将全随机输入生成的功能覆盖率收敛速度提高10倍以上,将约束随机输入生成的功能覆盖率收敛速度提高20倍以上. 相似文献
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论文基于UVM验证方法学,以及覆盖率驱动的芯片验证指导思想,搭建并分析了高度可重用的以太网控制器IP的验证平台.为了提高验证效率,论文对MAC的工作流程进行了研究,对其功能点进行了划分,针对性地编写了测试用例.在测试用例的驱动下,对MAC的数据收发功能进行了全流程的仿真验证.在大规模随机测试用例和定向测试用例的共同作用下,加快了验证所需要的时间,节省了仿真所需的计算机资源,达到了功能覆盖率100%的目标. 相似文献
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交易级建模技术适用于构建大规模电路系统的功能验证平台.结合C 天生的类继承机制和SystemC的接口通道机制,基于该建模技术的ATA控制器验证平台成功实现了随机化的交易级验证,降低了设计模块间通信的复杂度,结构上具有良好的可扩展性和可重用性.着重阐述该验证平台中抽象通道与适配器的通用设计方法,提出了一种基于面向对象技术的创新的验证平台设计模式,并分析了交易级建模和RTL建模之间的区别以及交易级建模技术在提高验证效率上的优势. 相似文献
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众核技术已成为当前处理器体系结构发展的必然趋势,如何对众核处理器设计进行有效而充分的验证,成为当今IC设计验证领域的研究热点之一,也是众核处理器芯片能否成功流片的关键因素之一。目前工业界采用基于仿真的验证作为主要的验证方式,重点介绍了以覆盖率为导向的RISC众核处理器的功能验证环境的整体设计,提出了“被动式”的验证思想,并采用“软硬件协同验证”的策略,最终达到每条指令都比对通过的验证目标,辅以后期阶段所引入的时序验证策略和功耗评估策略,完整地提出了一套芯片验证平台搭建和验证功能实现的方法流程。 相似文献
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Rawad Abou Assi Wes Masri Fadi Zaraket 《Software Testing, Verification and Reliability》2016,26(6):460-491
The goal of regression testing is to ensure that the behaviour of existing code, believed correct by previous testing, is not altered by new program changes. This paper argues that the primary focus of regression testing should be on code associated with (1) earlier bug fixes and (2) particular application scenarios considered to be important by the developer or tester. Existing coverage criteria do not enable such focus, for example, 100% branch coverage does not guarantee that a given bug fix is exercised or a given application scenario is tested. Therefore, there is a need for a new and complementary coverage criterion in which the user can definea test requirement characterizing a given behaviour to be covered as opposed to choosing from a pool of pre‐defined and generic program elements. This paper proposes this new methodology and calls it UCov, a user‐defined coverage criterion wherein a test requirement is an execution pattern of program elements, and possibly predicates, that a test case must satisfy. The proposed criterion is not meant to replace existing criteria, but to complement them as it focuses the testing on important code patterns that could go untested otherwise. UCov supports test case intent verification. For example, following a bug fix, the testing team may augment the regression suite with the test case that revealed the bug. However, this test case might become obsolete due to code modifications not related to the bug. But if a test requirement characterizing the bug was defined by the user, UCov would determine that test case intent verification failed. The UCov methodology was implemented for the Java platform, was successfully applied onto 10 real‐life case studies and was shown to have advantages over JUnit. The implementation comprises the following tools: (1) TRSpec: allows the user to easily specify complex test requirements; (2) TRCheck: checks whether user‐defined test requirements were satisfied, that is, supports test case intent verification; and (3) TRMigrate: migrates user‐defined test requirements to subsequent versions of a given program. Copyright © 2016 John Wiley & Sons, Ltd. 相似文献
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Martin Leucker Thomas Noll Perdita Stevens Michael Weber 《International Journal on Software Tools for Technology Transfer (STTT)》2005,7(2):184-194
We compare Haskell with Standard ML as programming languages for verification tools based on our experience developing the verification platform Truth in Haskell and the Edinburgh Concurrency Workbench (CWB) in Standard ML. We review not only technical language features but also the worlds of the languages, for example, the availability of compilers, tools, and libraries. We also discuss the merits and difficulties of comparing programming languages in this wide sense and support our view that Truth and the CWB are similar enough to justify the conclusions drawn in this paper. 相似文献
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Abdesselam Lakehal Ioannis Parissis 《Software Testing, Verification and Reliability》2009,19(2):133-154
LUSTRE is a data‐flow synchronous language, on which is based the SCADE tool‐suite, widely used for specifying and programming critical reactive applications in the areas of avionics, energy or transport. Therefore, testing LUSTRE programs, that is, generating test data and assessing the achieved test coverage, is a major issue. Usual control‐flow‐based test coverage criteria (statement coverage, branch coverage, etc.) are not relevant for LUSTRE programs. In this paper, a new hierarchy of adequacy criteria tailored to the LUSTRE language is presented. These criteria are defined on operator networks, which are usual models for LUSTRE programs. The criteria satisfaction measure is automated in LUSTRUCTU , a non‐intrusive tool (no instrumentation of the code), based on the symbolic computation of path activation conditions. The applicability and the relevance of the criteria are assessed on a case study. Copyright © 2008 John Wiley & Sons, Ltd. 相似文献
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曙光5000芯片组是曙光5000计算单元中的系统控制器,它通过HT接口连接两颗CPU并提供高速网络通信能力。为了确保曙光5000芯片组的功能正确性,我们为其设计了系统级功能验证平台SVP。SVP采用分层结构对系统进行建模,通过对本地计算单元的系统软件行为、硬件平台功能以及远程计算单元的网络行为进行模拟,提供了接近真实系统的验证环境。在曙光5000芯片组的验证过程中,SVP发现并排除了逻辑设计中的大多数功能错误,通过并行验证加速了验证覆盖率的收敛过程。 相似文献