The anomalous behavior of hydrogenated/unhydrogenated polysiliconthin-film transistors under electric stress

The characteristics of high-temperature processed thin-film transistors (TFT's) with/without plasma hydrogenation under the stress condition of V_ds=-15 V and V_gs=0 V have been investigated and compared. It is found that, after stress, the subthreshold swing is greatly improved for unhydrogenated TFT's but not for hydrogenated TFT's. Also, the off-state current is deteriorated for unhydrogenated TFT's but, on the contrary, it is improved for hydrogenated TFT's. A model that takes the effect of hydrogen passivation into account is proposed to interpret the anomalous behavior of TFT's under electric stress     

Bias temperature instability in hydrogenated thin-film transistors

The bias temperature instability is studied in hydrogenated n- and p-channel thin-film MOS transistors (TFT's) fabricated using a low-temperature process compatible with active matrix liquid crystal display application. We observe significant threshold voltage and subthreshold slope degradation under both positive and negative bias stress. The degradation increases with increased hydrogen incorporation and is temperature and electric field activated. The experimental results are explained based on trap creation model which depends on the hydrogen content of the device     

Self-aligned aluminum top-gate polysilicon thin-film transistorsfabricated using laser recrystallization and gas-immersion laser doping

We present electrical results from polysilicon thin film transistors (TFT's) fabricated using laser-recrystallized channels and gas-immersion laser-doped source-drain regions. A simple, four-level self-aligned aluminum top-gate process is developed to demonstrate the effectiveness of these laser processes in producing TFT's. The source-drain doping process results in source-drain sheet resistances well below 100 Ω/□. TFT field-effect mobilities in excess of 200 cm²/Vs are measured for the laser-fabricated unhydrogenated TFT's     

Performance improvement obtained for thin-film transistorsfabricated in prepatterned laser-recrystallized polysilicon

Thin-film transistors (TFT's) are fabricated in polysilicon films that are laser recrystallized either before or after active-area definition. We find the the performance of TPT's fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved. For example, the field-effect mobility is increased by a factor of three, the threshold voltage is reduced from 5.32 V to 0.07 V, and the subthreshold slope is cut in half for W/L = 10 μm/10 μm TFT's. All TFT's discussed utilize gas-immersion laser-doped source and drain junctions and are unhydrogenated     

Negative gate bias instability in polycrystalline silicon TFT's

Degradation of the device characteristics of poly-Si TFT's are seen following negative gate bias stress at elevated temperatures. The degradation has two components, One component is the trapping of holes in the gate oxide; this is a similar phenomenon to the so called `negative bias instability' seen in mono-Si MOSFETs. The other component is state formation and removal in the poly-Si bulk, or at the poly-Si-SiO₂ interface, and this is similar to that seen in αSi:H TFT's. The states formed are not the same as those produced by hot carrier stressing     

Estimate Threshold Voltage Shift in a-Si:H TFTs Under Increasing Bias Stress

A method of estimating threshold voltage shift in hydrogenated amorphous silicon (a-Si:H) transistors under increasing bias stress is proposed. Although the threshold voltage shift in a-Si:H thin-film transistor (TFT) has been modeled well under constant bias stress, its property with increasing bias stress, which occurs in many a-Si:H-based compensating circuits, still cannot be quantified without any restriction, such as constant overdrive bias or short stressing time. In this paper, we propose a model which is effective under an arbitrary increasing stress for a prolonged time. The proposed model reduces to the constant bias model if the stress bias remains unchanged. With this method, the lifetime of most compensating circuits based on a-Si devices can be estimated completely.      

Self-heating and kink effects in a-Si:H thin film transistors

We describe a new physics based, analytical DC model accounting for short channel effects for hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's). This model is based on the long channel device model. Two important short-channel phenomena, self-heating and kink effects, are analyzed in detail. For the self-heating effect, a thermal kinetic analysis is carried out and a physical model and an equivalent circuit are used to estimate the thermal resistance of the device. In deriving the analytical model for self-heating effect, a first order approximation and self-consistency are used to give an iteration-free model accurate for a temperature rise of up to 100°C. In the modeling of the kink effects, a semi-empirical approach is used based on the physics involved. The combined model accurately reproduces the DC characteristics of a-Si:H TFT's with a gate length of the 4 μm. Predictions for a-Si:H TFT's scaled down to 1 μm are also provided. The model is suitable for use in device and circuit simulators     

Activation energy of source-drain current in hydrogenated andunhydrogenated polysilicon thin-film transistors

The activation energy of the drain current in polysilicon thin-film transistors (TFTs) and the effects of hydrogenation on this energy are discussed. The activation energy data are fitted using different models of the density of states in the material. It is shown that a model which assumes a distribution of brand tail states and localized deep states can account for the activation energy data of unhydrogenated polysilicon TFTs. However, the activation energy data on hydrogenated TFTs cannot be explained with the band tail model. Instead, a simple model of deep states localized at the grain boundary can fit this data quite accurately. Also, it is shown that there is a characteristic kink in the activation energy data of the hydrogenated TFTs which is a signature of the location of the deep states relative to the valence band edge. Analysis indicates that these deep states are located approximately 0.36 eV from the valence band edge. This value is consistent with that obtained from absorption measurements using photothermal deflection spectroscopy     

Stability of short-channel P-channel polysilicon thin-filmtransistors with ECR N2O-plasma gate oxide

Stability of hydrogenated short-channel (⩽3 μm) p-channel poly-Si TFT's with very thin (12 nm) electron cyclotron resonance N₂O plasma gate oxide is investigated. The fabricated poly-Si TFT's with gate length not less than 2 μm show excellent stability characteristics of less than 0.1 V in the threshold voltage shift and less than 3% in the percent change of transconductance after harsh electrical stresses. In a small |V_G| stress, an effective shortening of channel length is observed due to trapping of hot-electrons and the minimum leakage current is decreased. However, a large |V_G| stress causes more degradation on the subthreshold slope and minimum leakage current due to trapping of hot-holes     

Gate-overlapped lightly doped drain poly-Si thin-film transistorsfor large area-AMLCD

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) polycrystalline silicon thin-film transistor (poly-Si TFT) applicable for large area AMLCD by employing the uniform and low-temperature doping techniques, such as ion shower doping and in situ doping. Experimental results show that the leakage current of the proposed TFT's is reduced by more than the magnitude of two orders, compared with that of conventional nonoffset TFT, while the ON current is scarcely decreased. It is verified by the device simulator that the electron concentration in the LDD region is increased under the ON state and decreased under the OFF state due to the field plate with gate potential over the LDD region. Furthermore, the vertical peak electric field in the LDD region is decreased significantly by the extended field plate potential during the OFF state. It is observed that the gate bias stress degrades significantly the subthreshold slope of the ion shower doped GO-LDD TFT's at the low drain bias but does not degrade the device characteristics of those with in situ doping due to the high-quality TEOS SiO₂ interlayer     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique     

Ageing of laser crystallized and unhydrogenated polysilicon thin film transistors

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and then laser crystallized using a single shot ECL (SSECL of SOPRA) with very large excimer laser. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine or diborane to fabricate n-type or p-type transistors respectively.These laser crystallized TFT's show poorer reliability properties than solid-phase crystallized TFT's. This poor stability is explained to originate from the high surface roughness produced by the laser crystallization, which is highlighted from Atomic Force Microscopy observations.Moreover to this conclusion, the behaviour of the threshold voltage shift ΔV_T during positive and negative stresses is checked to the light of a stretched exponential law that is, as supposed, a federative law. This law is explained in hydrogenated amorphous silicon TFT's by a dispersive diffusion coefficient of hydrogen in the disordered material. Taking into account that such relation appears as sufficiently general and, particularly, can describe the behaviour of monocrystalline silicon MOSFET and un-hydrogenated polysilicon TFT's where the hydrogen cannot involved, it can be supposed that it deals with disordered materials and disordered regions in crystalline materials (interface, grain boundary, …..).     

Plasma ion implantation hydrogenation of poly-Si CMOS thin-filmtransistors at low energy and high dose rate using aninductively-coupled plasma source

Defect passivation in polycrystalline silicon (poly-Si) CMOS thin-film transistors (TFT's) has been performed by plasma ion implantation (PII) hydrogenation process. Implantation at low energy (2 keV) and high dose rate(~10¹⁶/cm² S) was achieved by an inductively-coupled plasma source. The device parameter improvements are saturated in 3-4 min, which is much shorter than other hydrogenation methods reported in the literature. The stress measurements indicate that the devices hydrogenated by this new technique have much better long-term reliability than that hydrogenated by other techniques     

Self-passivated copper gates for amorphous silicon thin-filmtransistors

A solution to the amorphous silicon transistor gate metallization problem in active matrix liquid crystal displays (AMLCD's) is demonstrated, in the form of a self-passivated copper (Cu) process. Cu is passivated by a self-aligned chromium (Cr) oxide encapsulation formed by surface segregation of Cr in dilute Cu-10-30 at.%Cr alloys at 400°C, solving the problems of chemical reactivity during the plasma deposition, diffusion, poor adhesion to the substrate, and oxidation. The performance of self-passivated Cu bottom-gate thin-film transistors (TFT's) and their stability during thermal bias stress testing is comparable to that of Cr-gate reference TFT's. The gate line resistivity (including encapsulation) is 4.5 μΩ·cm at present     

Influence of mechanical bending and temperature on the threshold voltage instability of a-Si:H thin-film transistors under electrical stress

This paper studies the electrical characteristics of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) under flat and bending situations after AC/DC stress at different temperatures. Stress temperature was varied from 77 K to 400 K, and threshold voltage shifts were extracted to analyze degradation mechanisms. It was found that high temperature and mechanical bending played important roles under AC stress, with an enhanced stress effect resulting in a more serious degradation. This study also discusses the dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress.     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

Performance of thin-film-transistor-addressed liquid-crystal display circuits

The operation of thin-film-transistor (TFT)-addressed liquid-crystal (LC) display circuits is analyzed. The voltage on the storage capacitor in a simulated TFT-LC circuit is measured. TFT's fabricated in our laboratory have been demonstrated to be able to function satisfactorily in a TFT-LC circuit. The storage capacitor, thus the LC cell, can be charged to desired voltages within a line time and holds the voltage for one frame time under proper bias conditions. TFT's in a TFT-LC circuit perform differently from the dc condition. The dynamic ON current is higher and the dynamic OFF current is lower than the dc currents. Excellent dynamic stability in both on and off conditions is measured.     

A comparison of hydrogen and deuterium plasma treatment effects onpolysilicon TFT performance and dc reliability

We compare the performance and dc reliability of conventional top-gate, self-aligned polysilicon (poly-Si) thin-film transistors (TFT's) after passivation by plasma deuteration and conventional plasma hydrogenation. An optimum deuteration temperature of 300°C is found, as compared to 350°C for hydrogenation. Deuteration yields comparable TFT performance as hydrogenation, while deuterated TFT's exhibit increased resistance to threshold voltage degradation under dc stress. These results indicate that deuteration is a promising alternative to hydrogenation for achieving high-performance, high-reliability poly-Si TFT's for applications such as flat-panel displays     

High-performance laser-processed polysilicon thin-film transistors

We present electrical results from hydrogenated laser-processed polysilicon thin-film transistors (TFT's) fabricated using a simple four-mask self-aligned aluminum top-gate process. Transistor field-effect mobilities of 280-450 cm²/Vs and on/off current ratios of more than 10⁸ are measured in these devices. Except for the amorphous-silicon deposition step, the highest processing temperature that the substrate was subjected to was 350°C. Such good performance is attributed to an optimized laser-crystallization process combined with hydrogenation     

Narrow width effects of bottom-gate polysilicon thin filmtransistors

The effects of channel width on the characteristics of both hydrogenated and unhydrogenated bottom-gate polysilicon thin-film transistors (TFTs) were investigated in detailed. For unhydrogenated and silane gas formed TFTs, a drastic decrease in threshold voltage is observed due to the grain-boundary traps are reduced when the channel width is reduced to less than grain size, but the minimum drain current sensitive to intragranular tail states are nearly unchanged. After hydrogenation, almost grain boundary traps and intragranular tail states were passivated, the effect of traps along poly channel edges caused by the definition of poly channel pattern will dominate, i.e., threshold voltage and minimum drain current increase with decreasing channel width. Also disilane gas formed TFTs are studied for comparison