含约瑟夫森结电路的特性分析和研究

提出了超导约瑟夫森结模型(并联电阻—电容结模型)，给出了约瑟夫森效应的一些重要结果。在分析约瑟夫森结电路方程时，研究了其中出现的混沌特性和子台阶现象。计算获得的结果对混沌数字通信和超导电子学的应用将起到重要作用。     

约瑟夫森结的电路模型及其在超导电子学中的应用

为方便约瑟夫森结及其相关电路的仿真研究,根据约瑟夫森方程首次提出了约瑟夫森结的电路模型,给出了具体的电路原理图,并进行了封装.利用这个模型可以对约瑟夫森结的相关特性进行深入系统的仿真研究,这样不必自己编写程序对系统的微分方程进行数值求解,大大提高了工作效率.利用这个模型,对约瑟夫森结的混沌行为、相位锁定特性、RSFQ电路和SQUID进行了研究,结果说明了模型的正确性和实用性,模型的建立对于促进超导器件的相关研究具有一定意义.     

A Low-Noise 47-GHz Mixer Using a Permanent Josephson Junction

A new method to produce permanent Josephson junctions for millimeter-wave mixers is reported. In contrast to conventional point contacts which are mechanically unstable and require adjustments after each cooldown, these point contact junctions are set at room temperature, stay mechanically stable, and can be temperature cycled without readjustments. Using these junctions in a modified Sharpless wafer mixer mount, a single-sideband noise temperature of 71 K was measured at 47 GHz. Based on these results, system noise temperatures of less than 100 K are predicted for practical broad-band radiometers, RADAR, and communications receivers up to at least 100 GHz     

Bursting in adaptive hybrids

Adaptive echo cancellation is being used on shorter telephone circuits. However, while echo cancelers do tend to be effective on the shorter circuits, a new (and undesirable) phenomena called bursting has been observed. Bursting is characterized by long periods of successful echo attenuation alternating with short periods of wildly oscillating signals. The authors studied bursting by constructing a pair of simplified models of adaptive hybrid systems. The models are analyzed when they are excited by various DC and sinusoidal inputs, and the results are related back to the systems of interest, providing insight into the fundamental sources of the bursting problem-an imbalance of excitation and the enclosure of an adaptive filter in a feedback loop. Simulations providing corroborating evidence are discussed     

Bursting in the LMS algorithm

The least mean square (LMS) algorithm is known to converge in the mean and in the mean square. However, during short time periods, the error sequence can blow up and cause severe disturbances, especially for non-Gaussian processes. The paper discusses potential short time unstable behavior of the LMS algorithm for spherically invariant random processes (SIRP) like Gaussian, Laplacian, and K₀. The result of this investigation is that the probability for bursting decreases with the step size. However, since a smaller step size also causes a slower convergence rate, one has to choose a tradeoff between convergence speed and the frequence of bursting     

Disappearance of Fiske steps in Josephson fluxonic diode and Josephson fluxonic bipolar junction transistor

Fiske steps which are normally present in the I-V curve of Josephson junctions disappear if the junction is subjected to a magnetic field which reverses its direction at the center of the device as in Josephson fluxonic diode. Experimental results for small and long Josephson junctions are provided. It is proposed that the reversing magnetic field sets extra conditions at the center of the junction which makes the creation of standing electromagnetic waves impossible.     

On the Performance of Pulsed and Spiking Neurons

This tutorial paper presents an annotated overview of existing hardware implementations of Artificial Neural Systems based on Pulse Stream modulations, including also Spiking Neurons. Pulse Streams are quasi-periodic binary waveforms which convey analog information on waveform timing.The theoretical bases of Pulse Stream computation and multiplexing are shown for all the existing techniques. Pulse Stream modulations and multiplexing are then analyzed in terms of accuracy, response time, and both power and energy requirements. The performances of the various techniques are compared both with each other, and with those of other analog computing systems.     

The Josephson technology

The status of the superconductive Josephson technology is presented with emphasis on the activities related to the digital systems area. The important properties of the Josephson tehnology which make it potentially the highest performance technology are briefly, reviewed. After an introduction to the Josephson junction and devices, the system components such as logic, memory, and package are discussed. The chip fabrication process is reviewed and some experimental chips are described.     

Josephson shift registers

A review of Josephson shift-register circuits that have been designed, fabricated, or tested is presented with emphasis on work in the 1980s. Operating speed is most important, since it often limits system performance. Older designs used square-wave clocks, but most modern designs use offset sine waves, with either two or three phases. Operating margins and gate bias uniformity are key concerns. The fastest measured Josephson shift register operated at 2.3 GHz, which compares well with a GaAs shift register that consumes 250 times more power. The difficulties of high-speed testing have prevented many Josephson shift registers from being operated at their highest speeds. Computer simulations suggest that 30-GHz operation is possible with current Nb/Al ₂O₃/Nb technology. Junctions with critical current densities near 10 kA/cm² would make 100-GHz shift registers feasible     

Josephson Digital Devices and Circuits

A review of the progress in the field of Josephson digital devices and circuits is presented. Since the first report of measurements on the switching speed of a Josephson junction in 1966, a large variety of circuits have been developed, with one having a delay of only 13 ps. With miniaturization beyond the present 2.5-mu m linewidths, this remarkable speed probably can be exceeded. It is pointed out that the high speed is combined with very low power so that the high packing density needed to make use of the speed is possible. The paper reviews the Josephson junction and its incorporation into logic gates and memory cells. References are given to larger systems using these elements.     

Memory-cell design in Josephson technology

Operating principles and criteria for the design of Josephson memory cells are reviewed and the evolution of cell design is retraced to highlight the various constraints imposed by the requirement for high speed, density, large Operating margins, and ease of auxiliary memory circuit design. Two attractive cells have emerged so far. One is a nondestructive readout (NDRO) ring cell for a subnanosecond cache memory chip; the other a destructive readout (DRO) single-flux quantum cell for main memory applications. Both are presently being used as the basis for ongoing design work.     

Chaotic oscillations in Josephson tetrode

We numerically demonstrate the generation of chaos in a four-terminal superconductive device made of five Josephson weak-link junctions, which is referred to as "Josephson tetrode," for the applications of ultrafast random signal generations at frequencies of hundreds of gigahertz. In the Josephson tetrode, two junctions are series-connected and three junctions are parallel-connected. We calculate the dynamics of electrical voltages across the junctions when one of the normal resistances is varied. We confirm the generation of chaos by using a bifurcation diagram, three-dimensional attractors, and the Poincare sections. The bifurcation diagram can be interpreted as the quasi-periodicity-breakdown scenario to chaos. We clarify that the mechanism of the generation of chaos is a nonlinear frequency mixing among three independent voltages across the junctions. The condition of the generation of chaos can be predicted from the values of the coefficients in the equations of our model.     

Spiking in light pulses from GaAs Q-switched junction lasers

Using a detection system with 150-ps resolution, a spiking behavior has been detected in theQ-switched light output from GaAs junction lasers. At the lower currents in theQ-switching region, a single light spike, whose width is about 300 ps, is observed. At higher currents, additional light spikes appear whose widths and spacings decrease as the current is increased. At the highest pumping levels, only the initial spike is clearly resolved and its width has decreased to less than 200 ps. Qualitative agreement is obtained from a simple theory based on the standard rate equations. The necessary modifications to the theory are discussed and results of computer calculations are presented which predict that the width of the initial spike can be much less than 100 ps at sufficiently high pumping levels.     

The Josephson effect

This is a review of the Josephson effect in superconductors, with emphasis on the electrical properties of Josephson junctions and their application to devices and measurement techniques.     

Josephson serial-to-parallel decoder

We present the design and experimental demonstration of a 5-b serial-to-parallel decoder for a crossbar application. A serial train of seven bits is provided at the input with the first five being the code for selecting one of 32 output lines. The last two constitute the code that determines if the selected decoder in the crossbar switch should generate an output. Several circuit innovations were needed to meet the severe restrictions on power, current, and area required for the crossbar application. Operation of the circuit was demonstrated at 2 Gb     

A Josephson latch

A latch has been developed which is suitable for use in a high-speed Josephson latching-logic computer. Measurements on a test chip incorporating latch circuits have shown that the flip-flop is capable of changing states in ~120 ps and that races can be prevented by deriving timing information from the AC power waveform. Details of the design and experimental results are given.     

Josephson macrocell array

A modified variable-threshold logic (MVTL) gate for use in Josephson LSI circuits is considered. A 7.6 K-gate Josephison macrocell array whose functions can be changed by wiring changing has been developed. Automatic design problems, such as AC powering and small fan-outs, are solved by constructing the macrocell with a three-phase powering system and developing a magnetically coupled unit cell. The chip contains 21440 Josephson junctions on a 5 mm×5 mm die and is fabricated using 1.5 μm all-niobium Josephson techniques. An average delay of 5.3 ps/gate in the macrocell and a total chip power consumption of 23 mW have been obtained     

Josephson memory technology

Memory circuit architecture (decoder, cell, cell array, and sense circuit) is surveyed, with emphasis on implementing a memory with fast access and low power consumption. Recent progress in fabrication and circuit technology has improved memory performance. An AC powering scheme, instead of the earlier DC system, has been developed. The AC powering scheme eliminates complicated timing control, which restricts shortening access time, but introduces large power consumption and in-phase powering problems. A parallel decoding scheme that decreases the number of decoding stages is presented. It will decrease the decoding time and AND scheme decoder. An attractive OR-inverter scheme has been proposed for a decoder suitable for a memory with a large capacity. The chip performance strongly depends not only on whether the read mode is destructive or nondestructive but also on the cell connection method, which determines the line inductance. Because the cell input line inductance depends on layered construction of the lines, a planarizing technology for an Nb Josephson integrated circuit has been developed to reduce line inductance by thinning the insulators. Access time of less than 0.5 ns has been confirmed in 1-kb and 4-kb memories using the proposed memory architecture     

导航产业厚积薄发九大应用百花齐放

"目前导航产业在中国的发展态势,相当干PC产业发展到80286的时期."北京东方联星科技有限公司总经理张峻林,如是评价中国导航产业未来.