Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).     

High-Performance MIM Capacitors Using HfLaO-Based Dielectrics

Metal-insulator-metal (MIM) capacitors fabricated with (8%) La-doped HfO₂ single layer as well as HfLaO/ LaAlO₃/HfLaO multilayer dielectric stack are demonstrated. While the La-doped HfO₂ single layer is crystallized at 420^°C annealing, HfLaO/LaAlO₃/HfLaO multilayer dielectric stack remains amorphous. A high dielectric-constant value of 38 can be obtained when 8% La-doped HfO₂ is crystallized into cubiclike structure. However, it is observed that the linearity of MIM capacitor is degraded upon crystallization. The multilayer film has lower average dielectric constant but shows low quadratic voltage linearity of less than 1000 ppm/V² up to a capacitance density of 9 fF/?m² . It is observed that the HfLaO single-layer MIM is suitable for the applications with requirements of high capacitance density and robust reliability, while the multilayer MIM is suitable for a precision circuit.     

Embedded resistors and capacitors for organic-based SOP

System-on-package (SOP) architectures take advantage of compact, high-performance designs to place the maximum amount of functionality on a subsystem that can then be mounted on a lower-cost, lower density interconnect board. Embedding passive components is a key technology in achieving these goals since this enables smaller SOP substrate footprints or, equivalently, higher functional density, along with better power distribution, increased design flexibility and improved reliability. The resulting footprint areas of integrating capacitors will have more of an effect on the layer count of SOP assemblies than will integrating resistors due to the rather low specific capacitances of most embeddable dielectrics, but the situation is improving steadily. It may be necessary to use two different dielectric materials to cover the entire required range. The inherently lower parasitic inductance of embedded capacitors makes them much more useful in decoupling than surface mount capacitors, enabling more robust power distribution and decreased power/ground noise. The key to this performance enhancement in large boards is the use of a thin dielectric to decrease the inductance but, for the smaller SOP substrates, the dielectric constant must also be high to provide sufficient decoupling capacitance in the reduced area.     

Embedded thin film capacitors-theoretical limits

The large physical size of capacitors and/or excessive values of associated lead inductance are two major limitations in the development of novel packaging modules, with high packaging density, high performance and reliability along with low system cost. Embedded capacitor technology in thin film form offers a promising solution to these limitations. A design space with capacitance density and breakdown voltage as performance properties, with material dielectric constant and film thickness as parameters has been explored, focusing on tantalum pentoxide (Ta/sub 2/O/sub 5/) as the dielectric material. An inherent tradeoff is established between breakdown voltage and capacitance density for thin film capacitors. The validity of the proposed design space is illustrated with thin films of Ta/sub 2/O/sub 5/, showing deviation from the "best can achieve" breakdown voltage for films thinner than 0.4 /spl mu/m and films thicker than 1 /spl mu/m.     

Dual Process Dielectric Formation for Decoupling Capacitors on Flexible Substrates

Large area, high density integrated capacitors within printed wiring boards can provide a substantial decoupling capacitance with very low parasitic inductance. Tantalum pentoxide (Ta₂O₅) is an excellent dielectric for this application due to the relatively high dielectric constant (~ 22-24), however the difficulty of fabricating large, defect-free capacitors has thus far prevented the realization of practical applications. This work demonstrates high performance capacitors with Ta₂O₅ dielectric developed with a two step oxidation scheme consisting of reactive sputtering followed by anodization. Thin films of Ta₂O₅ were deposited by reactive sputtering on silicon and also on Upilex^reg covered glass wafers using dc magnetron sputtering with a gas flow ratio of 10/90 O₂/Ar. In the two-step oxidation scheme, anodization is performed after reactively sputtering tantalum oxide films to obtain a densifled oxide structure. The electrical and physical properties of these two step sputtered/ anodized tantalum oxide films are shown to be superior to those of tantalum oxide films prepared by either anodization or sputtering alone. This work has shown that Ta₂O₅ is a potential dielectric for integrated capacitors that could be used in advanced packaging applications.     

Power bus decoupling on multilayer printed circuit boards

Guidelines for the selection and placement of decoupling capacitors that work well for one-sided or two-sided printed circuit boards are not appropriate for multilayer boards with power and ground planes. Boards without internal planes take advantage of the power bus inductance to help decouple components at the higher frequencies. An effective decoupling strategy for multilayer boards must account for the low inductance and relatively high capacitance of the power bus     

Dielectric films for capacitor applications in electronic technology

In microelectronic applications, various approaches have been used to provide high capacitance thin film components. None of these has been widely accepted for reasons that are both technical and economic. Limited applications have been made of silicon and other simple oxides, e.g., of aluminum or tantalum, as dielectric media. Particularly in the area of microwave integrated circuits, requirements for high frequency, high specific capacitance, low to moderate loss, and integrability call for new thin film approaches. These requirements will only be met by using more complex compounds, possibly of ferroelectric materials. Aspects of material preparation, composition evaluation, and dielectric performance of thin film bismuth titanates are treated in a manner which should be of value in considering other complex dielectrics for similar use. Of particular technological importance is the use of thin silica barrier layers at the metal electrodes to permit achieving low dielectric loss.     

Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs

We measured and demonstrated the great advantages of embedded film capacitors in reducing power/ground inductive impedance and the suppression of SSN at frequencies up to 3 GHz for high-performance multilayer packages and PCBs. Eight-layer test PCBs were fabricated, and their inductive power/ground network impedances were measured as a function of film thickness, via distribution, and combined use with discrete decoupling capacitors, using a two-port self-impedance measurement method. This successfully demonstrated that the power/ground inductive impedance was reduced from 270 pH to 106 pH simply by using an embedded film capacitor instead of 16 discrete decoupling capacitors.     

多层陶瓷电容器的发展及其动向

小型、低压、大容量化，片式高压系列化和低成本化是当前多层陶瓷电容器的主要技术发展趋势；移动通信设备和开关电源等产品是其应用的热门。瓷膜材料的面世，符合多层陶瓷电容器的低成本、小型和大容量化的发展潮流，将会取得推广与应用。     

Integrating High-k Ceramic Thin Film Capacitors into Organic Substrates Via Low-Cost Solution Processing

Current organic package-compatible embedded decoupling capacitors are based on thick film (8-16 m) polymer-ceramic composites with dielectric constant (k) of 20-30 and do not have sufficient capacitance density to meet the impedance requirements for emerging high-speed circuits and high power density microprocessors. High-k/high capacitance density ceramics films that can meet the performance targets are generally deposited by high-temperature processing or costly vacuum technology (radio frequency sputtering, PECVD) which are expensive and also incompatible with organic packages. The objective of this project is to develop ultra thin films (100-300nm) with high dielectric constant using organic compatible processes to meet future decoupling applications. In the current study, direct deposition of crystalline ceramic films on organic boards at temperatures less than 100C was demonstrated with the hydrothermal method. Post-hydrothermal treatments were shown to minimize the defects in the as-synthesized hydrothermal barium titanate films and improve the breakdown voltage (BDV) and leakage characteristics. Thin films with high capacitance densities and breakdown voltages of 10V were demonstrated. As an alternate technique, sol-gel technology was also demonstrated to integrate ceramic thin films in organic packages. A major barrier to synthesis of sol-gel films on copper foils is the process incompatibility of the sol-gel barium titanate with the copper electrodes. To enable process compatibility, process variables like sol pyrolysis temperature and time, and sintering conditions/atmosphere were optimized. Capacitance densities above 1.1F/cm was demonstrated on commercial copper foils with a BDV above 10 V. The two technologies reported in this study can potentially meet midfrequency decoupling requirements of digital systems.     

Quantifying SMT decoupling capacitor placement in dc power-busdesign for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach     

Decoupling capacitors for multi-voltage power distribution systems

Multiple power supply voltages are often used in modern high-performance ICs, such as microprocessors, to decrease power consumption without affecting circuit speed. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is described in this paper. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. With the introduction of a second power supply, therefore, the interaction between the two power distribution networks should be considered. The dependence of the impedance and magnitude of the voltage transfer function on the parameters of the power distribution system is investigated. An antiresonance phenomenon is intuitively explained in this paper. It is shown that the magnitude of the voltage transfer function is strongly dependent on the parasitic inductance of the decoupling capacitors, decreasing with smaller inductance. Design techniques to cancel and shift antiresonant spikes out of range of the operating frequencies are presented. It is also shown that it is highly desirable to maintain the effective series inductance of the decoupling capacitors as low as possible to decrease the overshoots of the response of the dual-voltage power distribution system over a wide range of operating frequencies. A criterion for an overshoot-free voltage response is presented in this paper. It is noted that the frequency range of the overshoot-free voltage response can be traded off with the magnitude of the response.     

Ba_(0.5)Sr_(0.5)TiO_3薄膜电容的尺寸效应研究

采用射频磁控溅射和微细加工技术制备了不同尺寸的钛酸锶钡(Ba0.5Sr0.5TiO3,BST)平行板电容,研究了低频和高频条件下不同尺寸BST平行板电容的电容密度和Q值的变化情况。结果表明,由于存在边缘效应,BST薄膜电容的电容密度及Q值都具有尺寸效应。低频时,随着电容面积增大,电容密度减小,Q值增大。高频时,随着电容面积增大,电容密度及Q值减小。     

Highly reliable MIS capacitors with plasma nitridation and doubled dielectric-constant tantalum pentoxide

We studied effective thinning of metal-insulator-semiconductor tantalum pentoxide capacitors experimentally for DRAM application. First, we investigated the dielectric constant of a tantalum pentoxide film deposited and crystallized on an oxidation-resistant thick silicon-nitride film. Dependence of electrically equivalent thickness on physical thickness of tantalum pentoxide revealed an increased dielectric constant of 60, whereas the films on a silicon-dioxide film had a dielectric constant of no more than 40. To apply this increased dielectric constant to DRAM capacitors, we applied novel plasma nitridation on the surface of polysilicon. The plasma-nitrided surface showed fair oxidation resistance up to 800/spl deg/C, at which a tantalum pentoxide film fully crystallizes. The temperature was 100/spl deg/C higher than that of a conventional treatment using rapid thermal nitridation (RTN). The improved oxidation resistance enabled the increased dielectric constant as well as suppression of silicon oxide between the film and polysilicon. Consequently, effective thinning by 10% was demonstrated even on rugged polysilicon without increase of leakage current. Time-dependent dielectric-breakdown measurements revealed that the tantalum pentoxide capacitors fabricated using plasma nitridation are expected to have a lifetime three orders of magnitude longer than that of those fabricated using RTN.     

Tunable barium strontium titanate thin film capacitors for RF andmicrowave applications

The measurement results for thin film barium strontium titanate (BST) based voltage tunable capacitors intended for RF applications are reported. At 9 V DC, BST capacitors fabricated using MOCVD (metalorganic chemical vapor deposition) method achieved 71% (3.4:1) tunability. The measured device quality factor (Q) for BST varactors is comparable with the device Q for commercially available varactor diodes of similar capacitance. The typical dielectric loss tangent was in the range 0.003-0.009 at VHF. Large signal measurement and modeling results for BST thin film capacitors are also presented     

Influence of a floating plane on effective ground plane inductancein multilayer and coplanar packages

The impact of a floating metal layer on the effective ground plane inductance has been investigated in both multilayer (ground planes) and coplanar (ground conductors) packages. For the multilayer case, both thick and thin film geometries were examined, and the results were compared to a thin film coplanar configuration. It was seen that the floating plane actually increases the ground plane inductance in the multilayer case and decreases the ground plane inductance in the lead frame case. Examining the current density in the floating and ground plane and the ground's partial self-inductance and ground-signal partial mutual inductance give a detailed explanation for this phenomenon     

Wide-Tunable Low-Field Interdigitated Barium Strontium Titanate Capacitors

This letter reports low-field wide-tunable interdigitated barium strontium titanate (BST) capacitors. The capacitors consisting of BST thin film dielectric, silicon substrate, and gold metallization have been fabricated. The capacitance exhibits 0.2 pF at zero-bias and shows a tunability of 63% with an applied electric field of 1.4 V/mum. This corresponds to a 3.5 mum electrode gap width and a 5 V dc bias. Microwave measurements reveal a zero bias film quality of 50 around 30 GHz.     

RF, DC, and Reliability Performance of MIM Capacitors Embedded in Organic Substrates by Wafer-Transfer Technology (WTT) for System-on-Package Applications

In this paper, radio frequency (RF), dc, and reliability performance have been studied on metal-insulator-metal (MIM) capacitors embedded in organic substrates. The MIM structure including ~74-nm SiN dielectric was prefabricated on Si and then transferred onto organic substrates (FR-4) by wafer-transfer technology (WTT). The RF characteristics up to 30 GHz were investigated by equivalent lumped circuit modeling, showing that the parameters associated with the MIM layers including the main capacitance, parasitic inductance, and resistance were only slightly changed by the WTT process. The substrate-related parasitics were reduced as a result of the replacement of lossy Si with insulating FR-4 substrates. Excellent capacitance linearity, low voltage coefficient (~2.2 ppm/V²), and temperature coefficient (~38 ppm/degC) were obtained for capacitors on FR-4 substrates. Current-voltage and time-dependent dielectric breakdown tests verified that, after the harsh processes of WTT, the MIM structures maintained the intrinsic reliability as those originally fabricated on Si. This paper, along with earlier reports, proved that WTT presented a new dimension to realize embedded capacitors for high-density circuit board and system-on-package applications     

Tera Tool [terahertz time-domain spectroscopy]

The terahertz differential time-domain spectroscopic method is applied to characterize the dielectric and optical properties of a variety of thin films at terahertz frequency. The results of several samples including silicon dioxide, parylene-n polymer film, tantalum oxide film, and protein thin layer samples were presented. The dielectric property of silicon dioxide thin film is well fitted to that of a bulk. The dielectric properties of parylene-n thin films show good agreement with the result measured by the goniometric terahertz time-domain spectroscopy. The dielectric and optical properties of the tantalum oxide show reasonable data with previously available data. Some properties in thin films are slightly different from the bulk materials. The origin of this discrepancy is considered due to fine grain formation, mechanical stresses, formation of interfacial layers, or rough interfaces during thin-film deposition process. The terahertz differential time-domain spectroscopy may be applied to the measurement of the dielectric and optical properties of thin films (nanometer to micrometer) of several materials, which cannot be done by any other method.     

Electrical characteristics of anodic tantalum pentoxide thin films under thermal stress

In this work, we report on electrical characteristics of tantalum oxide films fabricated by anodic oxidation of tantalum nitride and tantalum silicide with thicknesses ranging from 100 to 4500 Å. These films exhibit greatly improved leakage currents, breakdown voltage and a very low defect density, thus allowing the fabrication of large area capacitors. Leakage currents in the insulator under thermal stress have been carefully studied in order to determine the nature and physical origin of the dominant conduction mechanisms in the insulator. We have found noticeable differences in the dominant conduction mechanisms for thin and thick anodic tantalum pentoxide films. These differences are explained in terms of the thickness dependence of the insulator layer structure.