Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-/spl mu/m CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-/spl mu/A quiescent currents and /spl plusmn/1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal.     

Simple technique using local CMFB to enhance slew rate and bandwidth of one-stage CMOS op-amps

A simple modification to a one-stage op-amp for operation as a class AB amplifier leads to significant slew rate and bandwidth enhancement with essentially equal silicon area and static power dissipation requirements. Experimental results of a prototype in 0.5 /spl mu/m CMOS verify SR and bandwidth enhancement factors of almost one order of magnitude.     

A Power‐Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two‐stage power‐efficient class‐AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low‐power dissipation and low‐voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class‐AB amplifier. The design is fabricated using 0.18‐μm CMOS technology.     

Winner-Take-All Class AB Input Stage

A novel technique to implement class AB differential amplifier input stages is proposed. It is based on the use of Winner-Take-All circuits for achieving dynamic current boosting, and is well suited for low-voltage operation. Experimental measurements of an OTA using this technique, fabricated in a 0.5-μm CMOS technology, show a slew rate of 92 V/μs for an 80-pF load and 120 μW of static power consumption.     

Micropower CMOS S&H circuit for ambient intelligence applications

A novel sample and hold (S&H) circuit is presented based on the use of a class AB CMOS operational transconductance amplifier with very high slew rate and very low static power consumption. The circuit has been fabricated in a 0.5 /spl mu/m double-poly CMOS technology. The quiescent power consumption is only 80 /spl mu/W using a dual supply voltage of /spl plusmn/1.35 V. The S&H occupies 0.075 mm/sup 2/ of silicon area.     

A tiny, high-speed, wide-band, voltage-feedback amplifier stablewith all capacitive load

A tiny, high-speed, wide-band, voltage-feedback operational amplifier capable of driving unlimited capacitive load is described. A class AB input stage is combined with a modified dynamic Witch-Hazel current mirror to provide high slew rate and wide bandwidth with a small die area and small idle current. An RC network couples part of the capacitive load into the high-impedance node, therefore lowering the dominant pole and increasing stability as a function of capacitive load. The part was fabricated on a 3 GHz, 40 V complementary bipolar process. The quiescent current of the chip is 4.5 mA with 1500 V/μm slew rate and a -3 dB bandwidth of 235 MHz. The part is operational from ±2.5 V to ±18 V supply range. Die size is 38 mils by 46 mils and it fits into a tiny surface outline transistor (SOT) package     

Ultra Low Power Improved Differential Amplifier

In this paper, a low voltage and ultra low power operational transconductance amplifier (OTA) is presented. As will be shown, the transient response and open loop gain of the proposed OTA are improved using adaptive biasing and DC gain enhancement techniques. The contributions of the proposed OTA are ultra low power consumption (only 3.977 μw), low supply voltages (±0.6 V), high swing, high speed, and high gain. It can clearly be seen that for the proposed OTA, the gain of the differential half-circuit in the input stage (A _d ), DC gain (A ₀), gain bandwidth (GBW), and slew rate (SR) are increased, whereas the settling time (T _S ) is decreased. The results of simulations done using 0.18 μm Silterra CMOS process technology and the measurement results are presented to validate and compare the advantages of this work and other related works.     

一种新的套筒式全差分跨导放大器设计

A novel fully differential telescopic operational transconductance amplifier （OTA） is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18 μm CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced.     

A wide-band, low-power, high slew rate voltage-feedback operationalamplifier

A wide-band low-power voltage-feedback operational amplifier on a 3 GHz, 40 V complementary bipolar technology is described. The class AB input stage takes advantage of some current-boost transistors which enhance and linearize the slew-rate during large-signal operation without increasing the power consumption. The triple-buffered output stage provides 100 mA of load current maintaining good linearity. Since the circuit design and technology development were concurrent, several different circuits were stepped into one wafer to fully characterize the process and identify the best product candidates. The low-current version of this chip has a quiescent current of 2.5 mA, 2000 V/μs slew rate and gain bandwidth of 110 MHz. The medium-current version draws only 6.5 mA of current at the same supply voltage while the slew rate increases to 3500 V/μs and bandwidth to 210 MHz. Both parts are operational from +/-2.75 V to +/-18 V supply range. Die size is 51 mils by 76 mils on a poly-emitter CB process     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿（CEC）技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿(CEC)技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

Two CMOS Current Feedback Operational Amplifiers

Two internally compensated CMOS current-feedback operational amplifiers are discussed in this paper. The circuits are entirely made up of class AB stages, thereby increasing slew rate and drive capability, avoiding many of the drawbacks incurred by previous CMOS and even bipolar implementations. Experimental results on one prototype fabricated in a 0.35-mum process using a 20-pF load and supplied with 3.3 V are also given, showing, as main performance parameters, a SR of 35 V/mus and a constant closed-loop bandwidth (in inverting configuration with a 10-kOmega feedback resistor) of about 2 MHz.     

Design and analysis of high Transconductance Current Follower Transconductance Amplifier (CFTA) and its applications

In this paper, a single-stage class AB bulk-driven amplifier operating in weak inversion region is proposed. The presented amplifier benefits from an improved high input swing structure using quasi-floating-gate technique. The composite transistors and recycling configuration used at the input stage enable the input differential pair to operate under low supply voltages with larger transconductance as compared to the conventional models at no expense of power budget. The circuit is designed in 0.18 µm CMOS technology and simulation results show 61.5 dB low frequency gain with the gain bandwidth of 30.15 kHz and 55.3 V/ms average slew rate. The total current of 275 nA and 0.6 V supply voltage make the proposed amplifier a suitable choice for ultra-low-power applications.     

恒跨导高摆率轨对轨运算放大器的设计

本文在分析MOS管恒跨导输入级和AB类输出级运算放大器的基础上设计了一个高摆率、恒跨导的轨对轨运算放大器。在输入级中采用了齐纳二极管的稳压原理,保证Rail-to-Rail运算放大器的输入跨导恒定。为了实现高转换率,本文采用了一种新型的压摆率提高电路。另外,为了提高系统的稳定性,采用了控制零点的米勒补偿进行频率补偿。采...     

High current efficiency single-stage bulk-driven subthreshold-biased class-AB OTAs with enhanced transconductance and slew rate for large capacitive loads

This paper introduces two high-performance single-stage bulk-driven (BD) operational transconductance amplifiers (OTA) in weak-inversion with rail-to-rail input and output voltage ranges suited for the excessively low-voltage of 0.5 V supply. The strategy depends on adopting a modified bulk-driven non-tailed input core to achieve high input core transconductance with a minimum power supply and an enhanced input common-mode range. Moreover, a partial positive feedback loop provides an overall improved DC gain and effective transconductance further. The input core of OTA1, named composite class-AB OTA, comprises two combined non-tailed differential pairs as composite differential pairs. The proposed OTA2, named composite super class-AB BD-OTA, exploits a matched bulk-input Flipped voltage follower (FVF) pair to adaptively bias the input core used in the composite class-AB BD OTA. As a result, a significant increase in large-signal input current to the output side due to super class-AB behavior improves the slew rate. The post-layout simulation results using the Cadence Spectre simulator with UMC 0.18 µm process technology confirm that the proposed OTAs have improved small-signal and large-signal performances over the conventional OTA driving a high capacitive load of 5 nF. The proposed composite class-AB and super class-AB BD OTA deliver 2.29 times, and 3.77 times open-loop DC gain, 10.6 times, and 117 times unity-gain bandwidth with 2 times, and 12.03 times slew rate at the expense of almost 0.52 times and 1.21 times power consumed over conventional counterpart, respectively.

     

Efficient Slew-Rate Enhanced Operational Transconductance Amplifier

Today, along with the prevalent use of portable equipment, wireless, and other battery powered systems, the demand for amplifiers with a high gain-bandwidth product (GBW), slew rate (SR), and at the same time very low static power dissipation is growing. In this work, an operational transconductance amplifier (OTA) with an enhanced SR is proposed. By inserting a sensing resistor in the input port of the current mirror in the OTA, the voltage drop across the resistor is converted into an output current containing a term in proportion to the square of the voltage, and then the SR of the proposed OTA is significantly enhanced and the current dissipation can be reduced. The proposed OTA is designed and simulated with a 0.5 m complementary metal oxide semiconductor (CMOS) process. The simulation results show that the SR is 4.54 V/s, increased by 8.25 times than that of the conventional design, while the current dissipation is only 87.3%.     

一种具有高转换速率的轨对轨运算放大器

为了驱动液晶显示器背板形成不同的灰阶,设计了一种利用齐纳二极管的稳压原理,实现恒定跨导用于TFT-LCD液晶显示的片内运算放大器。采用互补差分输入级,实现了Rail-to-Rail的共模电压输入范围;一种新颖的转换速率增强结构,加快了运算放大器的响应速度;输出级采用Class AB类控制电路,并将其嵌入到求和电路中,以保证较低的噪声和失调。直流增益为101dB,单位增益带宽为13MHz,相位裕度为64°。仿真结果证明该运算放大器工作良好,其面积为500μm×380μm。     

A high CMRR, class AB, fully differential current output stage

A true class ‘AB’ fully differential current output stage with very high common mode rejection ratio is presented in this study. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by SPICE simulation in TSMC 0.18 μm CMOS, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high common-mode rejection ratio (CMRR), high slew rate, high current drive capability, high output compliance, and very low power consumption while operating at power supply of ±0.9 V. The interesting results such as current drive capability of ±100 μA, high output voltage swing of ±0.8 V, low static power consumption of 21 μW, and very high CMRR of 84.5 dB is achieved utilizing standard CMOS technology. The performance of circuit at the presence of process and voltage variations evaluated through corner case and Monte Carlo analysis. The harmonic distortion is evaluated to investigate the circuit’s linearity. The transient stepwise response analysis is also done to verify the stability of proposed class ‘AB’ FDCOS.     

Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS

A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a G _m boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of \(2\,\frac{{\text{V}}}{{\text{V}}}\), this voltage combiner can produce gain more than \(5\,\frac{{\text{V}}}{{\text{V}}}\). So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than \(55^{\circ }\) for a typical load of 10 pF. The input referred noise is \(150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}\) at 10 Hz and slew rate \(0.02\,{\text{V}}{/}\upmu{\text{s}}\) for 10 pF load.     

Adaptive-biased buffer with low input capacitance

A new analogue buffer, which is a differential-pair-based level shifter followed by an adaptive-biased cascode source follower, is proposed. The structure exhibits low input capacitances, enhanced slew rate, high bandwidth and low distortion. The simulated results have shown input capacitance of 99.5 fF at 1 MHz, slew rate of 55.5 V/μs, -3 dB bandwidth of 37.9 MHz, and THD less than 1% for 1 Vpp input signal up to 6 MHz at a 100 kΩ//15 pF load. The buffer consumes 2.4 mW at 5 V supply in a 0.8 μm n-well CMOS technology