基于改进五输入择多门的QCA全加器设计及应用

量子元胞自动机(Quantum-dot cellular automata,QCA)是一种新兴的纳米技术.本文基于改进的五输入择多门,设计出一个全加器,在保持正确逻辑功能的基础上较以往的全加器有一定优势.应用该全加器设计加法器和乘法器,结果表明在某些性能上有显著提高.     

基于量子元胞自动机容错全加器的设计

为提高新一代纳米器件量子元胞自动机(QCA)电路的稳定性及可靠性,提出了一种容错1位全加器,然后通过QCADesigner软件来仿真分析1位容错全加器,验证了该设计的可行性及它具有较好的容错性,该设计对复杂QCA电路的容错性的研究起到借鉴作用.     

基于量子元胞自动机容错反相器的设计

分析了由线、反相器、扇出、择多逻辑门等量子元胞自动机组成的基本电路在工艺制造过程中可能存在的故障,基于块择多逻辑门的冗余结构设计思想,设计出具有容错能力的量子元胞自动机反相器,最后利用QCADesigner软件对位于不同输入输出点的极化值进行了仿真研究和验证。结果表明,所设计的反相器结构对称,输入与输出方式多样性,对元胞位移故障和元胞缺陷故障具有较好的容错能力,这将对构成更复杂的大规模QCA集成电路容错的研究具有一定的借鉴意义。     

基于量子元胞自动机的新型同或门结构设计北大核心

由于互补金属氧化物半导体（CMOS）器件尺寸的限制,量子元胞自动机（QCA）成为有望替代CMOS的新兴纳米器件。量子元胞自动机具有超低功耗、超高速度和高密度结构的潜在优势。提出了一种新型的同或门结构,在面积、延迟、复杂度及功耗方面相较于之前的结构均存在优势。所提出的新型同或门结构仅使用28个面积为0.02μm^2的QCA元胞,延迟仅为0.75个时钟周期。为了检验提出的设计在大型复杂QCA电路中的性能,实现了4,8和16位的奇偶校验器电路。模拟结果表明,所设计的电路性能各方面均优于先前的设计。     

基于QCA的五输入Majority门设计及应用

Majority门作为多数逻辑电路的基本逻辑单元,其性能直接影响整体电路的质量.使用量子元胞自动机（QCA）设计Majority门具有结构简单的优点.本文提出了一种三层电路实现五输入Majority门的设计,并以此设计了全加器,进一步应用于多位加法器和乘法器中,与已发表的电路设计比较表明,其版图使用面积和元胞数有明显的减少,加法器元胞数和面积改进最高可达43%和87.2%,乘法器元胞数和面积改进最高可达48.2%和100%.     

量子元胞自动机全加器的性能分析与设计

作为一种新型的纳米器件,量子元胞自动机（Quantum-dot cellular automata,QCA）有望取代传统CMOS器件.本文总结了目前已提出的三种全加器（Full Adder,FA）架构,通过概率转移矩阵（Probabilistic Transfer Matrix,PTM）分析找出其中最稳定的架构,进一步地,利用这三种全加器分别构建串行加法器,并从复杂度、不可逆功耗、成本等方面进行比较,结果发现性能最优的全加器架构为MR Azghadi FA.随后,选择该架构提出了一种针对全加器的新型逻辑门和共面QCA全加器电路,并应用此全加器设计了多位串行加法器,经对比分析表明,本文所提出的全加器电路在面积、元胞数和功耗等方面均有较大改进,且具有很好的扩展性.     

基于量子元胞自动机的逻辑电路

简述了量子元胞自动机 (QCA)的理论及其逻辑电路的实现方式。每个量子元胞包含两个电子 ,它们通过库仑相互作用与邻近元胞耦合。每个量子元胞上的电荷分布趋于沿两垂直轴的某一轴向分布 ,可以以此来表达二进制信息。用这些量子元胞的阵列来实现各种逻辑门     

两点量子元胞自动机逻辑电路设计与仿真

择多逻辑门和反相器是量子元胞自动机(QCA)逻辑电路的基本组件。设计了两点量子元胞自动机(两点QCA)的传输线、择多逻辑门和反相器等基本逻辑器件。通过仅在信号沿竖直方向传递需要取反时用到水平放置元胞的设计,使电路布局更加紧凑。利用这些基本逻辑器件完成了一位数值比较器电路的设计。基于两点QCA系统的半经典模型,利用遗传模拟退火法对电路功能进行了仿真。仿真结果显示,两点QCA同样能够有效实现传统四点QCA的功能,而其所需的电子数和量子点数均减少了32.1%,电路集成度提高了49.4%。     

基于量子元胞自动机的奇偶校验系统分块设计

量子元胞自动机(QCA)是一种纳米范围内不含晶体管的计算范例。基于QCA提出了QCA奇偶校验系统电路的分块设计方法。首先设计了异或门、奇偶判断单元,再运用分块设计思想构建了奇数产生电路和奇偶校验电路的结构,所设计的电路拥有尺寸极小和功耗极低等优点,QCADesigner软件仿真结果验证了设计的有效性。     

量子元胞自动机全加器的布尔差分测试法

根据布尔差分测试法的基本原理以及量子元胞自动机(QCA)的缺陷特性,提出一种适用于QCA的测试方法。以QCA 1位全加器为例,采用QCA Designer软件,验证该方法的有效性与可行性,并与Tahoori等人提出的QCA电路测试法进行比较。结果表明,新设计的布尔差分测试法具有高故障覆盖率和易测性等优点,对未来复杂QCA电路的测试有一定的借鉴作用。     

Single-Bit Comparator in Quantum-Dot Cellular Automata (QCA) Technology Using Novel QCA-XNOR Gates

To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor (CMOS) technology developers. The scaling scenario is not an option nowadays and other technologies need to be investigated. The quantum-dot cellular automata (QCA) technology is one of the important emerging nanotechnologies that have attracted much researchers’ attention in recent years. This technology has many interesting features, such as high speed, low power consumption, and small size. These features make it an appropriate alternative to the CMOS technique. This paper suggests three novel structures of XNOR gates in the QCA technology. The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology. The proposed structures are used as the main building blocks for a single-bit comparator. The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature. The comparison results are encouraging to append the proposed structures to the library of QCA gates.     

基于量子细胞自动机的全加器实现

基于量子细胞自动机的双稳态特性和数字电路,设计了异或门和加法器,采用半经典仿真方法对其进行了仿真,并与Tougaw等人设计的异或门和全加器进行了比较,结果显示在能实现同样的异或和加法功能的情况下,电路结构较为简单且使用的QCA数目大大减少,在规模上只有Tougaw设计的电路的一半左右,这对于减小以后设计的更复杂电路的规模有较大的借鉴意义。     

Design and Optimization of Full Comparator Based on Quantum‐Dot Cellular Automata

Quantum‐dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA‐based circuits.     

基于量子元胞自动机的PLA故障分析和检测

量子元胞自动机(quantum-dot cellular automata,QCA)可编程逻辑阵列(programma-ble logic array,PLA)结构可用于实现大规模可编程逻辑电路。分析了4种故障类型发生在PLA单元的8个区域中的影响,得出了具体的影响效果。其中,直接或间接致使隐含线和与门发生逻辑错误的故障均会导致PLA中故障所在行整行失效,其他故障只会影响故障所在的PLA单元的逻辑功能和配置,而对PLA中的其他单元没有影响。此外,基于故障分析,提出了具体的PLA故障检测方法。     

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata(QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder(ESDBA) is 26% faster than the carry flow adder(CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder(EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead(CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of(N-1)+3.5 clock cycles compared to the N*One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.     

基于QCA可编程逻辑阵列单元的元胞缺陷研究

介绍了一种量子元胞自动机(QCA)可编程逻辑阵列结构,该结构可用于实现量子元胞自动机大规模可编程逻辑电路,采用QCADesigner仿真软件研究了元胞缺失、移位缺陷和未对准缺陷对可编程逻辑阵列单元逻辑功能的影响。得出了特定结构下,每个元胞移位缺陷和未对准缺陷的最大错位距离,以及导线模式中存在特定位置的8个可缺失元胞。这为缺陷单元的应用提供了一个具体的参数标准,提高了PLA阵列的单元利用率。