基于ADMM的惩罚函数构造方法优化

为了提升传统交替方向乘子法(Alternating Direction Method of Multipliers,ADMM)惩罚译码算法的误码性能和收敛速率,对罚函数做进一步优化,提出一种基于三段式罚函数的ADMM惩罚译码算法(Three-Segment ADMM-Penalized Decoding,TS-ADMM-PD)。通过引入过渡函数,其斜率介于前后两段函数之间,达到折衷译码性能和收敛速度的目的。优化后的罚函数在x=0和x=1附近斜率较大,以增强对伪码字的惩罚力度,降低误码率并加快译码收敛;在x=0.5附近斜率较小,以便此处的变量节点信息进行传递。仿真结果表明,相比于I-ADMM-PD算法,所提的TS-ADMM-PD算法有着更优秀的误码性能和收敛速度。     

基于变量节点更新的交替方向乘子法 LDPC惩罚译码算法

基于交替方向乘子法(ADMM)的改进惩罚函数LDPC译码算法能够提升译码性能,但其所需优化参数过多且性能提升有限。针对该问题,将该算法与其它带有惩罚函数的译码算法比较后发现,两者的不同之处仅在于译码算法中变量节点的更新规则不同。因此,该文通过构造一种新的变量节点的更新方法去减少优化参数数目并提升译码性能。实验仿真表明,相较于原有算法,该文所提算法有效减少了所需优化的参数数目,此外,所提算法的平均迭代次数更少且能实现约0.1 dB的性能提升。     

基于变量节点可靠度的洗牌置信传播算法

提出了一种新的低密度奇偶校验(Low-Density Parity-Check,LDPC)码串行译码策略.该方法基于原有的LDPC码串行译码策略,根据来自信道的初始消息的可靠度对变量节点或校验节点进行均匀分组.对所提方法的误码率与平均迭代次数进行了分析.仿真结果表明:该策略的性能比原来的LDPC码串行译码策略有很大提高.     

LDPC码的信道自适应迭代译码算法

中短长度LDPC码采用BP迭代译码时,在低信噪比区,大量的经过多次迭代仍不能纠正的错误帧造成了平均迭代次数的大大增加;在中高信噪比区,比特对数似然比值的振荡造成了译码性能的降低。为了减少低信噪比区的平均迭代次数,提高中高信噪比区的译码性能,本文提出了一种LDPC码的信道自适应迭代译码算法。该算法采用基于校验和错误模式的预判决机制和消息加权平均算法,通过低信噪比区预判决机制的主导作用来减少平均迭代次数,通过中高信噪比区消息加权平均算法的主导作用来抑制因比特LLR值振荡而形成的错误帧,从而实现译码算法与信道变化特征的自适应,提高了译码效率。仿真结果显示,相对于BP译码算法,该译码算法在低信噪比区减少了平均迭代次数而译码性能没有显著变化,在中高信噪比区提高了译码性能而平均迭代次数没有明显增加。     

多元LDPC码分层译码算法及其在QPSK调制下的应用

文章将二元LDPC码对数域的分层译码算法成功运用在多元LDPC码的译码过程当中。仿真结果表明,在理想加性高斯白噪声信道环境下,QPSK调制时,多元LDPC码分层译码算法的性能明显优于传统的对数域译码算法,因此它可以有效提升消息传递算法的收敛速度,减少译码延时。     

基于CMMB标准准的LDPC码动态译码算法研究

针对低密度奇偶校验码(LDPC)的置信传播算法(BP)、分层算法(LBP)在迭代过程中以随机的节点顺序更新,不能快速达到收敛的特点,本文详细分析了一种选择可靠度小的节点先更新的动态译码算法,并以应用于CMMB标准的LDPC码进行性能仿真.与LBP算法相比,动态算法的译码收敛速度明显提高,译码的平均迭代次数减少50%.最后对动态算法的译码复杂度进行了分析.     

基于分组排序的码率兼容打孔LDPC码BP译码算法

由于在一定码率范围均能获得良好的误码性能,码率兼容打孔LDPC(rate-compatible punctured LDPC,RCP-LDPC)码成为时变信道下优选编码方案。然而,与非打孔码相比,RCP-LDPC码的BP译码收敛速度太慢。为了提高译码收敛速度,提出一种基于打孔变量点分组优化和串行调度的BP译码算法。根据BP译码消息的可靠度对打孔变量点进行排序和分组,使其在译码时,按可靠度由高到低的次序依次更新各组变量点消息。仿真结果表明,当最大译码迭代次数较低时,本文方法的误码性能优于BP算法和随机分组洗牌BP算法。特别是当打孔比特较多时,性能改善越明显。     

多元LDPC码列分层DBC译码算法

针对多元LDPC码扩展最小和（Extended Min Sum,EMS）译码算法收敛速度慢、运算复杂度高的问题,提出一种多元LDPC码列分层动态检泡（Dynamic Bubble-Check,DBC）译码算法。首先对变量节点按不同列重进行分层处理,译码时率先更新列重较大分层的变量节点消息,不同层之间采用串行方式进行消息传递,通过并串结合的方式降低译码迭代次数。在校验节点消息更新过程中,采用动态检泡方法减少EMS算法中的运算量,降低算法复杂度。仿真结果表明,在几乎不损失性能的前提下,该算法的平均最大迭代次数仅为EMS译码算法的50%,复杂度降低为EMS算法的50%。     

一种动态加权的LDPC译码方法

为了加快低密度奇偶校验（LDPC）码的译码速度,有效改善LDPC码的译码性能,针对校验节点更新过程中的对数似然比（LLR）值的大小,设计了一种LDPC码的动态加权译码方法。以IEEE 802.16e标准的奇偶校验矩阵为例,根据LLR值的变化规律,利用增长因子和抑制因子对和积译码算法和最小和译码算法进行动态加权。仿真结果显示,基于动态加权的译码方法相对于传统译码方法误码率都有明显改进,译码复杂度也有所降低。     

一种改进的LDPC码译码算法

文中提出了一种改进的基于加权错误校验的LDPC码比特反转算法,该算法不需要软信息,译码时采用了设定判决门限的方法,减少了译码过程中的迭代次数和译码复杂度.仿真结果表明:对于高Girth、低码率的LDPC码,该算法达到了比多种利用软信息的比特反转算法更少的迭代次数和更优异的性能.     

Operation reduced low‐density parity‐check decoding algorithms for low power communication systems

Decoding operation reduction algorithms on min‐sum layered low‐density parity‐check (LDPC) decoders are proposed in this paper. Our algorithm freezes selected operations in high reliable nodes to reduce power while preserving error correcting performance. Both memory accesses and active node switching activities can be reduced. A novel node refresh mechanism reactivates frozen nodes to minimize coding gain degradation. We propose three decoding operation reduction algorithm variations to trade‐off complexity and operation reduction for LDPC decoders with different degrees of parallelism and memory requirement. Simulation results show that the number of LDPC decoding operations is reduced across all SNR ranges. The decoding convergence speed is not affected. Hardware architecture and FPGA implementation for IEEE 802.16e LDPC codes are presented. Copyright © 2011 John Wiley & Sons, Ltd.     

一种基于交错行列消息传递的LDPC码改进译码算法

为进一步改善低密度奇偶校验(LDPC)码译码算法的纠错性能,并加快其译码的收敛速度,提出一种基于交错行列消息传递的改进译码算法.该算法通过将动态调度策略译码算法中的残差值思想引入到串行调度译码算法中,使得串行调度译码算法在每次迭代进行消息更新前都会进行一次残差值排序的计算,并对其节点消息原有的固定更新顺序进行重新排序.仿真结果表明:在误码率为10-4时,该改进的译码算法相比于行消息传递算法和列消息传递算法有0.25和0.24 dB的增益;在误码率为10-5时,相比于交错行列消息传递算法有0.13 dB的增益.     

Design of Quasi-Cyclic LDPC codes based on Euclidean Geometries

A new method for constructing Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes based on Euclidean Geometry (EG) is presented. The proposed method results in a class of QC-LDPC codes with girth of at least 6 and the designed codes perform very close to the Shannon limit with iterative decoding. Simulations show that the designed QC-LDPC codes have almost the same performance with the existing EG-LDPC codes.     

Optimization of LDPC codes for modulation and detection in layered multi-antenna architectures

In this paper we first perform the density evolution of LDPC codes in layered multi-antenna architectures using bitinterleaved coded modulation and detection based on successive decoding and interference cancellation. The noise thresholds of LDPC codes are shown to be achieved within 1.2 dB of the capacity for these architectures. We then present a rate allocation method which optimizes the performance of a layered architecture and find good degree distributions for LDPC codes with the rates allocated by our method. Simulation results show that the performance for an optimized layered architecture is better by 4 dB than that for the layered architecture using LDPC codes with the same rate in all layers.     

High-Throughput Layered LDPC Decoding Architecture

This paper presents a high-throughput decoder architecture for generic quasi-cyclic low-density parity-check (QC-LDPC) codes. Various optimizations are employed to increase the clock speed. A row permutation scheme is proposed to significantly simplify the implementation of the shuffle network in LDPC decoder. An approximate layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. The computation core is further optimized to reduce the computation delay. It is estimated that 4.7 Gb/s decoding throughput can be achieved at 15 iterations using the current technology.      

A high‐performance belief propagation decoding algorithm for codes with short cycles

The simplicity of decoding is one of the most important characteristics of the low density parity check (LDPC) codes. Belief propagation (BP) decoding algorithm is a well‐known decoding algorithm for LDPC codes. Most LDPC codes with long lengths have short cycles in their Tanner graphs, which reduce the performance of the BP algorithm. In this paper, we present 2 methods to improve the BP decoding algorithm for LDPC codes. In these methods, the calculation of the variable nodes is controlled by using “multiplicative correction factor” and “additive correction factor.” These factors are obtained for 2 separate channels, namely additive white Gaussian noise (AWGN) and binary symmetric channel (BSC), as 2 functions of code and channel parameters. Moreover, we use the BP‐based method in the calculation of the check nodes, which reduces the required resources. Simulation results show the proposed algorithm has better performance and lower decoding error as compared to BP and similar methods like normalized‐BP and offset‐BP algorithms.     

High Performance Non-Binary Quasi-Cyclic LDPC Codes on Euclidean Geometries LDPC Codes on Euclidean Geometries

This paper presents algebraic methods for constructing high performance and efficiently encodable non-binary quasi-cyclic LDPC codes based on flats of finite Euclidean geometries and array masking. Codes constructed based on these methods perform very well over the AWGN channel. With iterative decoding using a Fast Fourier Transform based sum-product algorithm, they achieve significantly large coding gains over Reed-Solomon codes of the same lengths and rates decoded with either algebraic hard-decision Berlekamp-Massey algorithm or algebraic soft-decision K?tter-Vardy algorithm. Due to their quasi-cyclic structure, these non-binary LDPC codes on Euclidean geometries can be encoded using simple shiftregisters with linear complexity. Structured non-binary LDPC codes have a great potential to replace Reed-Solomon codes for some applications in either communication or storage systems for combating mixed types of noise and interferences.     

Quasi-cyclic LDPC codes using overlapping matrices and their layered decoders

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have the parity-check matrices consisting of circulant matrices. Since QC LDPC codes whose parity-check matrices consist of only circulant permutation matrices are difficult to support layered decoding and, at the same time, have a good degree distribution with respect to error correcting performance, adopting multi-weight circulant matrices to parity-check matrices is useful but it has not been much researched. In this paper, we propose a new code structure for QC LDPC codes with multi-weight circulant matrices by introducing overlapping matrices. This structure enables a system to operate on dual mode in an efficient manner, that is, a standard QC LDPC code is used when the channel is relatively good and an enhanced QC LDPC code adopting an overlapping matrix is used otherwise. We also propose a new dual mode parallel decoder which supports the layered decoding both for the standard QC LDPC codes and the enhanced QC LDPC codes. Simulation results show that QC LDPC codes with the proposed structure have considerably improved error correcting performance and decoding throughput.     

基于平均概率和停止准则的多元LDPC码加权符号翻转译码算法

为了提高多元低密度奇偶校验(LDPC, low density parity-check)码符号翻转译码算法的性能并降低译码的复杂度,提出了基于平均概率和停止准则的多元LDPC码加权符号翻转译码(APSCWSF, average probability and stopping crite-rion weighted symbol flipping)算法。该算法将校验节点邻接符号节点的平均概率信息作为权重,使翻转函数更加有效,提高符号的翻转效率,进而改善译码性能。并且通过设置迭代停止准则进一步加快算法的收敛速度。仿真结果显示,在加性高斯白噪声信道下,误符号率为10?5时,相比WSF算法、NSCWSF算法(Osc=10)和NSCWSF算法(Osc=6),APSCWSF算法(Osc=10)分别获得约0.68 dB、0.83 dB和0.96 dB的增益。同时,APSCWSF算法(Osc=6)的平均迭代次数也分别降低78.60% ~79.32%、74.89% ~ 75.95% 和67.20% ~70.80%。