基于FPGA的π/4DQPSK跳频调制器的设计与实现

将π/4DQPSK调制与跳频技术相结合,设计了π/4DQPSK跳频调制器。利用FPGA实现了 π/4DQPSK基带跳频调制,并由AD9957完成正交调制、数模转换和一次上变频。设计了 乒乓 方式上变频调制器完成二次上变频及跳频调制。实测结果表明,跳频频率误差小于1 Hz ,换频时间小于2 μs, 瞄准干扰信噪比为8 dB时,误码率低于10-4。     

一种基于倒“T”形贴片结构的WLAN天线设计

提出了一种基体背面有电磁带隙结构的倒“T”形双频微带天线。研究发现该天线具有双频带特性,其双频工作频率分别为2.4 GHz和5.2 GHz,相应的带宽为805 MHz (2.099~2.944 GHz) 和831 MHz (4.568~5.409 GHz),增益达到3.1 dBi。仿真和测试结果基本吻合,表明该天线可以很好地满足WLAN工作频段标准要求,具有很好的应用前景。     

一种改进的小型化超宽带平面倒锥缝隙天线

提出了一种改进的超宽带平面倒锥缝隙贴片天线,通过调整倒锥缝隙和倒锥贴片的形 状,在更小尺寸条件下,实现了超宽带性能。天线总体尺寸为40 mm×40 mm× 1.5 mm。采用仿真软件分析了该天线的阻抗带宽、辐射方向图及增益特性。结果显示,该 天线的回波损耗小于-10 dB的带宽为2.2 GHz到大于16 GHz,在低频段具有全 向性,在3～14 GHz频段增益随频率的变化在4～7 dB之间。     

单偏振光纤声光调制器

该文介绍了一种全光纤耦合的单偏振声光调制器的设计及应用。理论分析了光纤声光调制器的工作原理,描述了单偏振光纤声光调制器的关键指标(插入损耗、消光比、光脉冲上升时间)的设计方法和单偏振光纤准直器的耦合工艺方法。设计制作了工作在1.06 μm波长的高速低插损单偏振光纤声光调制器,其偏振消光比达到42 dB,能有效隔离系统偏振噪声。     

宽带短波技术在测量船中的应用

针对现有岸船短波通信系统存在的数据传输速率低、多业务支持能力弱等问题,提出了一种宽带岸船短波通信系统。在应用数字调制技术和正交频分复用(OFDM)技术后,系统接收机灵敏度由-74 dBW降到了-91 dBW,数据传输率由9 kbit/s提升为50 kbit/s。对宽带岸船短波通信系统与其他岸船通信系统的多网融合潜力进行了分析,为新一代岸船通信网的建立提供了思路。     

带引向器的非对称平衡对拓Vivaldi天线设计

设计了一副改进的非对称平衡对拓Vivaldi天线。辐射贴片外边缘用3阶多项式曲线修正,以实现很宽的阻抗带宽。在天线口径处嵌入一个金属贴片作引向器以改善天线的辐射特性。对辐射贴片引入非对称性,使得E面波束偏离得到进一步补偿。实测结果表明,该天线具有极宽的工作带宽,在2~40 GHz内的增益大于0 dBi,且在15~30 GHz内的增益大于14 dBi;E面的波束偏离在6~40 GHz频率范围内小于3°。该天线具有结构简单、尺寸紧凑（44 mm×98 mm）以及方向图稳定等优点。该天线能够较好地应用于相控阵、超宽带系统等。     

0.1～4 GHz达林顿-共射共基结构的增益模块

提出了一种新型电路拓扑结构的增益模块,该增益模块为达林顿-共射共基结构,对 其工作原理进行了分析。基于AWR Microwave Office软件的仿真结果表明：达林顿晶体管共 射放大电路具有较强的电流放大能力,能有效提高增益;共基放大电路能抑制电路密勒效应 ,改善电路高频响应。设计了增益模块的版图,用2 μm InGaP/GaAs HBT工艺成功流片 ,测试结果表明：在01～4 GHz频率范围内,该增益模块最大增益为25 dB,最小 增益大于13.5 dB,在900 MHz工作频率时,该增益模块的P1dB为20 d Bm。     

B3G射频接收机前端设计

分析了DC-OFDM零中频接收方案,采用两个相邻子载波以分路/合路的方式进行信号处理以降 低硬件难度和复杂度。利用ADS软件设计了B3G射频接收机,其低噪声放大器的最低噪声系数 为1.7 dB,三阶交调点为-1 dBm;下变频器在频带范围内其增益为12.5 dB, 1 dB压缩点-12 dBm,三阶交调点-3 dBm。实验 测试结果表明,所设计的前端满足接收机的指标要求,适合于宽带通信系统。     

一种SIR结构的超宽带带通滤波器

提出了一种基于阶梯阻抗谐振器（Step Impedance Resonator,SIR）结构的具有平行耦合微带线的超宽带（Ultra-wideband,UWB）带通滤波器。滤波器采用孔径补偿技术设计,在地面上蚀刻两个矩形槽,以增强顶层微带线之间的耦合。为了优化S参数并改善带外的抑制,在谐振器中采用了缺陷微带结构（Defective Microstrip Structure,DMS）。仿真结果表明,滤波器的通带范围为2.3~6.1 GHz,中心频率为4.2 GHz,分数带宽（Fractional Bandwidth,FBW）大于90.4%;插入和回波损耗分别优于-1 dB和-10 dB;通带中群延迟的变化范围为0.4~0.6 ns,滤波器的线性度良好。该滤波器可用于5G通信系统。     

一种高频谱纯度的C频段宽带频率合成器设计

为了提高频综的频谱纯度,提出了一种新型多级子谐波混频锁相环的设计方法,研制了一款超低相噪频综。介绍了该频综的设计方案,分析了关键技术,仿真和论证了相位噪声和杂散抑制等主要指标,最后对该频综进行了研制和实际测试。测试结果如下：工作频率为4 500~7 600 MHz,频率步进小于1 kHz,相位噪声优于-123 dBc/Hz@25 kHz,频率切换速度小于75 μs,杂散抑制大于70 dB,均满足设计要求,设计方案比较合理可行。采用该方法设计的频综具有小步进、低相噪、换频速度快、低杂散等特点,可用于高性能电子战接收机中,具有广阔的应用前景。     

High Average-Efficiency Multimode RF Transmitter Using a Hybrid Quadrature Polar Modulator

This paper presents a hybrid quadrature polar modulator (HQPM) to drive the power amplifier (PA) highly efficiently in a wireless RF transmitter required for multimode operation. For enhancing the transmit efficiency, a switching-mode PA realized as Class-E design is used in the transmitter. The HQPM consists of a quadrature modulator for processing the RF modulated carrier and a Class-S modulator for processing the supply-voltage signal. The quadrature modulator and the Class-S modulator deliver the output signals with proportional envelope variation before being inserted into the RF-input terminal and the supply-voltage terminal of a Class-E PA, respectively, causing the double envelope modulation to distort the modulated RF signal at the PA output. Therefore, a digital predistorter is embedded in the HQPM for compensation. The proposed HQPM-based transmitter can help reducing the average dc and input RF powers and the output feedthrough levels so as to enhance power added efficiency and adjacent channel power rejection remarkably.     

Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation

A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate f_max are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate f_s and a SB-DAC, respectively. By proper selection of the hysteresis in the comparator and the ratio F = f_s/f_max, the performances of both modulators are shown to be equivalent. The comparator with hysteresis and the loop filter produce, in the modulator output, a limit cycle of frequency /max which is modulated by the input signal. Therefore, the modulator output can be considered to be a pulsewidth (PW) modulated signal with a frequency approximately equal to /max, and the proposed modulator is called a PW-SDM. Despite the high sampling rate of the comparator output, the integrators and the SB-DAC of the proposed modulator have the same speed requirements as those of the equivalent conventional MB-SDM. On the other hand, in the proposed modulator there are not MB (analog-to-digital or digital-to-analog) converters. Therefore, for a given set of specifications, the proposed PW-SDM is expected to consume less power and area than its equivalent conventional MB modulator.     

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.     

Asynchronous Sigma-Delta analog-to digital converter based on the charge pump integrator

The concept of the asynchronous Sigma-Delta analog-to-digital converter (ASD-ADC) based on the charge pump integrator is discussed in the paper. A two-level conversion scheme is utilized. The first level is accomplished by amplitude-to-pulse-width mapping in the asynchronous Sigma-Delta modulator. The other level consists in the time-to-digital conversion. The ASD-ADC belongs to a class of mean value converters since the digital outputs correspond to the mean values of the input signal in time windows of varying width. The configurations of the charge pump modulator either with bipolar, or with unipolar controlled current sources are presented. The design of the charge-pump-based modulator model using classical solutions of bipolar technology is exemplified. The input/output simulation results of the designed asynchronous Sigma-Delta modulator (ASDM) are reported. Next, the design of the time-to-digital converter, the analysis of the quantization error, and two concepts of the converter digital output interface are presented. The comparison of the minimum transmission bit rate of the serial output port(s) for both concepts is carried out. Finally, the procedure of evaluation of the ASD-ADC key design parameters for speech signal supporting a possible original input signal recovery is exemplified.     

Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.     

Picosecond pulse response of broad-band guided-wave interferometric light modulators

Picosecond pulse operation of the guided-wave light modulator is reported in this paper. First, we analyze the time responses of phase and intensity modulators of the traveling-wave type, and the modulated output waveforms related to the modulating pulses are discussed. It is shown that there is an optimum interaction (or electrode) length of the modulator whereby the drive voltage is minimized for a desired output pulse width. The traveling-wave push-pull light intensity modulator of Ti-diffused LiNbO3waveguides was modulated by a pulse train of 1 GHz repetition frequency, and the modulated output was observed by the image tube streak camera modified for sinusoidal scan at the same frequency. The duration of the modulated light pulses was less than 45 ps, which shows good agreement with the predicted one.     

A noise-shaped switching power supply using a delta-sigma modulator

A technique to reduce in-band tones in switch-mode power supplies is described. It takes advantage of the noise-shaping properties of the delta-sigma (/spl Delta//spl Sigma/) modulator to eliminate the spikes normally present in switching power supplies. A framework is introduced for comparing the conventional pulsewidth modulated (PWM) controller and this approach. A buck converter test circuit is constructed that is designed for a PWM controller clocked at 200 kHz and then substituted with a /spl Delta//spl Sigma/ modulator controller clocked at 400 kHz. The RMS noise power of the PWM controller is 14.9 mW compared to the rms noise power for the /spl Delta//spl Sigma/ modulator of 75.85 mW measured in a 2-MHz bandwidth. Although the /spl Delta//spl Sigma/ modulator rms noise power is higher, the noise floor is below the tones seen at the output of the PWM controller. A multibit /spl Delta//spl Sigma/ modulator controller, however, provides a significant reduction in the spectral output of the power supply. Values of 3.75 and 0.24 mW rms noise power are observed at the output of a 2-bit and 4-bit /spl Delta//spl Sigma/ modulator controller, respectively.     

Accurate Time-Domain Simulation of Continuous-Time Sigma–Delta Modulators

In this paper, we present a methodology for the simulation of continuous-time (CT) sigma-delta converters. This method, based on a fixed-step algorithm, permits not only a time-domain simulation of the modulator output but also the simulation of intermediary signals. The method is based on the discretization of the CT models and the use of a discrete simulator such as Simulink, which is more efficient than an analog simulator. By using filters with a sampling frequency that is higher than the modulator output frequency, the model can simulate input signals with a bandwidth that is higher than half the modulator sampling frequency. The transformation is exact in terms of noise transfer function and asymptotically exact in terms of signal transfer function (the transfer function from the modulator input to each stage filter output rapidly tends to the CT-model transfer function when the number of steps increases).     

A novel auto-bias control scheme for stabilizing lithium niobate Mach-Zehnder modulator at any operating point

In this paper,we propose and experimentally demonstrate an auto-bias control scheme for stabilizing a lithium niobate（LN）Mach-Zehnder modulator（MZM）at any operating point along the power transmission curve.It is based on that the bias drift would change the operating point and result in varying the output optical average power of the Mach-Zehnder modulator and its first and second derivatives.The ratio of the first to the second derivative of the output optical average power is used in the proposed scheme as the key parameter.The experimental results show that the output optical average power of the LN MZM hardly changes at the desired operating point,and the maximum deviation of output optical average power is less than±4%.     

Hybrid delta-sigma ADC

A hybrid (analog/digital) architecture is proposed to implement a robust high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a scaling block and a high-order single-bit digital modulator. The combination simplifies the realization of the analog modulator, and it allows the use of most of its full-scale input range.