An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability

An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented. This unified CAD methodology builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance. A number of circuit experiments are included to extract the contributions of key MOSFET parameters and physical layout sensitive parasitic elements from circuit simulation results. This CAD setup thus allows easy and detailed comparison of different technologies, device models, and LPE tools to prevent possible bugs in the software as well as inaccuracies in device and parasitic models and timing tools. The software code to carry out the circuit simulations, analysis, and display of the results in an automated fashion has been specifically developed to support this framework. Some of the experiments designed for this work are also placed on the product chip for model-to-hardware correlation. The comparison of the hardware data to the model predictions points to the sources of any discrepancies and aids in tuning the product design to reflect changes in the technology as part of an overall design for manufacturing (DFM) platform     

Clock distribution networks in synchronous digital integratedcircuits

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed     

Wave-pipelining: a tutorial and research survey

Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical oddity into a realistic, although challenging, VLSI design method. This paper presents a tutorial of the principles of wave-pipelining and a survey of wave-pipelined VLSI chips and CAD tools for the synthesis and analysis of wave-pipelined circuits     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

Measuring the uniqueness and variety of analog circuit design features

Analog circuit design activity is currently a less formalized process, in which the main source for innovation is the designer's ability to produce new designs by combining basic devices, sub-circuits, and ideas from similar solutions. There are few systematic methods that can fuse and transform the useful features of the existing designs into new solutions. Moreover, most automated circuit synthesis tools are still limited to routine tasks, like transistor sizing and layout design. Developing new design techniques that can combine the existing design features requires metrics that describe the uniqueness and variety of the features. This paper evaluates for analog circuits two such general-purpose metrics proposed in [1] and [2]. Three case studies are discussed on using the metrics to characterize the design features of current mirrors, transconductors, and operational amplifiers. The two metrics and the presented study is useful in producing an overall characterization of analog circuit features. This can help in enhancing the circuit design process, training of young designers, and developing new automated synthesis tools that can explore more solution space regions that are likely to include novel design features.     

Concurrent fault simulation on message passing multicomputers

Even though hardware accelerators are common in very large scale integration (VLSI) computer-aided design (CAD), fault simulation is a notable exception because of limited availability of memory, the need for dynamic memory management and the complexity of the algorithms themselves. Although simplified fault simulation algorithms that assume a zero delay circuit model can be accelerated, their applicability is limited. Most application specific integrated circuits (ASIC's) designed in industry today have on-chip memory blocks of different dimensions and characteristics, enhancing the complexity of a fault simulator. In this paper, we present a multiple delay algorithm for concurrent fault simulation of logic gates and functional memory blocks. This algorithm has been implemented on the microprogrammable accelerator for rapid simulation (MARS) hardware accelerator system with a 22 MHz clock and a capacity to simulate circuits with millions of devices. Speedup factors of 20 to 30 are easily achieved when compared to software simulators running on comparable hardware platforms and using identical circuit models     

Applications of asynchronous circuits

A comparison with synchronous circuits suggests four opportunities for the application of asynchronous circuits: high performance, low power; improved noise and electromagnetic compatibility (EMC) properties, and a natural match with heterogeneous system timing. In this overview paper each opportunity is reviewed in some detail, illustrated by examples, compared with synchronous alternatives, and accompanied by numerous pointers to the literature. Conditions for applying asynchronous circuit technology, such as the existence and availability of computer-aided design (CAD) tools, circuit libraries, and effective test approaches, are discussed briefly. Asynchronous circuits do offer advantages for many applications, and their design methods and tools are now starting to become mature     

Efficient logic-level timing analysis using constraint-guidedcritical path search

As the operating speed of digital circuits dramatically increases with the advance of VLSI technology, it is becoming more critical to ensure that the circuits are free from timing-related design errors. In a traditional static timing approach nonfunctional paths cannot be distinguished from functional ones since the functionality of a circuit is ignored. This often results in overestimation of circuit delay and can degrade the circuit performance. In today's design methodology where the use of automated logic synthesis and module-based design are popular, circuits with a very large number of nonfunctional (false) paths are common. This paper describes an efficient logic-level timing analysis approach that can provide an accurate delay estimate of a digital circuit which may have many long false paths. By using logic incompatibilities in a circuit as constraints for critical path search, the algorithm determines the longest sensitizable path without explicit path enumeration. Since the number of false paths that can be implicitly eliminated is potentially exponential to the number of path constraints, performance improvement is significant     

A metal-oriented layout structure for CMOS logic

A design method is described for the realization of large digital modules of random logic for custom integrated circuits in CMOS technology. The layout structure is based on the gate matrix concept with a metal orientation instead of a polysilicon orientation. The symbolic layout is obtained by using 11 different microcells with simple assembly rules. It is derived from the functional specifications of the circuit (Karnaugh maps) using a very simple and attractive method. A CAD program for translating the symbolic layout into a geometrical one is described. It works by assembling geometrical microcells. The advantages and disadvantages of the metal-oriented structure are analyzed through examples of industrial designs. The technique is not suitable for fast circuits. However, it results in an improvement of productivity by a factor of about four and a packing density for large modules which is at least comparable with that of nonoriented hand layouts.     

Simulating EM fields

Software tools for simulating and analyzing electromagnetic (EM) fields are described, with particular reference to integrated circuits (ICs). The use of a three-tiered approach for large-scale design is discussed, and a different tool is needed at each level. The most prudent approach today is to solve small pieces of a large problem and use a linear circuit simulator to combine the S-parameter files from the subnetworks. Several such simulators are described. A table of representative software packages is included     

Computer-aided design of large-scale integrated I/SUP 2/L logic circuits

Thanks to the simple, regular structure of its basic gates, integrated injection logic (I/SUP 2/L) is particularly suited to automated design (CAD) procedures for evolving large-scale integrated digital circuits. This paper describes CAD methods for I/SUP 2/L circuits that permit the use of existing, tried CAD programs, and illustrates their application in the design of the I/SUP 2/L basic gate, computer simulation of I/SUP 2/L logic circuits, interconnection pattern generation, and preparation of a final layout plan.     

ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of Analog integrated circuits

The ARIADNE approach to computer-aided synthesis and modeling of analog circuits is presented. It is a mathematical approach based on the use of equations. Equations are regarded as constraints on a circuit's design space and analog circuit design is modeled as a constraint satisfaction problem. To generate and efficiently satisfy constraints, advanced computational techniques such as constraint propagation, interval propagation, symbolic simulation, and qualitative simulation are applied. These techniques cover design problems such as topology construction, modeling, nominal analysis, tolerance analysis, sizing and optimization of analog circuits. The advantage of this approach is the clear separation of design knowledge from design procedures. Design knowledge is modeled in declarative equation-based models (DEBMs). Design procedures are implemented into general applicable CAD tools. The ARIADNE approach closely matches the reasoning style applied by experienced designers. The integration of synthesis and modeling into one frame and the clear separation of design knowledge from design procedures eases the process of extending the synthesis system with new circuit topologies, turning it into an open design system. This system can be used by both inexperienced and experienced designers in either interactive or automated mode.     

Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

A fully integrated timing generator for the picturephone video-telephone camera

All the timing intervals necessary for a video-telephone camera have been derived from a multivibrator oscillator by a digital process. These include camera blanking, horizontal and vertical sync, sweep triggering, clamp disable, and locked 2:1 interlace. The timing generator consists of a multivibrator and a pulse-delaying circuit using tantalum integrated RC timing elements and silicon integrated circuits. Output signals are derived digitally using resistor-transistor logic, which best meet the requirements of small size, low power, and producibility while providing adequate noise margin. These logic design considerations are discussed. The complete timing generator has been realized using five beam-leaded silicon and two tantalum integrated circuits including 217 transistors, 345 resistors, and capacitors totaling 4000 pF, all mounted on one square inch of ceramic.     

Methodical aspects of logic synthesis

The increasing complexity of integrated circuits demands improved design quality. For system developments with small- or medium-scale integrated circuits, successive steps of the design process are interconnected loosely. Therefore, design checks, tests, and even redesigns could be performed without affecting large fractions of the overall design. With large scale integration (LSI) and especially very large scale integration (VLSI), the situation has changed drastically. The technological capability of these techniques allows designers to put a whole digital system on a few chips or even on one single chip. Consequently, all design steps between the definition of the system and its realization as a semiconductor structure must be strongly interconnected to yield successful and economic solutions. Reduced possibilities for testing and correcting design errors do not permit design concepts that follow the principle of trial and error. But up to now, the so-called logic design has been dominated by manually generated solutions. Because of the inherent possibilities of misinterpretation of the design task or of local design errors, analytical tools like simulation have to demonstrate the correctness of a design. But the restricted model accuracy, incomplete sets of test data, and excessive request for computing time are limiting factors of this design strategy in the context of VLSI. Therefore, other concepts for logic design are necessary that avoid analytical tools as much as possible but support the design process by synthesis. This paper discusses some methodical aspects of this problem, and it mentions some properties of logic design tools that are of practical importance.