Measurements and modeling of the DC temperature dependence of electrical conductivity in thin films of lead phthalocyanine

Many of the phthalocyanines exhibit p-type conductivity, and electrical conductivity through thin films of these materials having ohmic contacts show space-charge-limited conductivity (SCLC) dominated by trap levels located within the band gap. In the present work evaporated thin films of lead phthalocyanine with ohmic gold electrodes were prepared, which showed two distinct regions in the dependence of current density J on applied voltage V. At low voltages sample conductivity was ohmic, changing at higher voltages to a square-law dependence of J on V, which is indicative of SCLC dominated by trap levels located at a single discrete energy level. The results of temperature measurements indicate three distinct regions, in each of which the hole concentrations are controlled by different activation energies. A simple model is proposed in which a single trap level is located at the same energy spacing E_t from the valence band edge as a single acceptor level. This predicts three different temperature ranges, two of which correspond to those covered by the experimental results. The experimental results indicate a trap level located at an energy E_t = 0.36 eV above the valence band edge and a thermal band gap E_g = 1.51 eV. Using the proposed model together with data from the experimental J-V characteristics, an acceptor concentration of 4.85 × 10¹⁹ m ^− 3 and a trap concentration of 5.18 × 10²⁵ m^− 3 are indicated. Measurements of mobility based on this model yield a value of 2.6 × 10^− 4 m² V^− 1 s^− 1, which is in close agreement with previous work.     

Electrical transport mechanisms and photovoltaic behavior of 2-(2-furanylmethylene) propanedinitrile/p-Si heterojunction

Au/2-(2-furanylmethylene) propanedinitrile/p-Si heterojunction was fabricated using conventional thermal evaporation technique. Current density–voltage (J–V) characteristics of the heterojunction were investigated at different temperatures. Tunneling conduction mechanism in the lower voltage range was identified from the forward bias (J–V) characteristics. The calculated value of the change of built-in voltage with respect to the absolute temperature is (−1.88 × 10⁻³ V K⁻¹). At higher voltages, a space charge limited current (SCLC) mechanism controlled by an exponential trapping distribution above the valence band edge was observed. The total concentration of traps was found to be 8.077 × 10²¹ m⁻³. Under reverse bias, the conduction mechanism is due to thermally generated carriers in the lower voltage range and the Poole–Frenkel effect is observed in the higher voltage range. The heterojunction showed a photovoltaic behavior under illumination with an open-circuit voltage of 0.19 V and a short-circuit current density of 102.7 mA m⁻².     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.     

Electrical conduction mechanisms of metal nanoclusters embedded in an amorphous Al2O3 matrix

We present the synthesis and electrical characterization of amorphous nanocomposite layers made of metallic nanoclusters embedded in an alumina matrix (nc-Co:Al₂O₃). The nanostructured materials were fabricated using a pulsed laser deposition (PLD)-derived method based on a nano-cluster generator coupled with a conventional PLD system for host medium co-deposition. The films were subjected to a detailed structural study carried out using high-resolution transmission electron microscopy and atomic force microscopy. The clusters inserted in the alumina matrix are metallic, well crystallized and possess an fcc structure with an average diameter centered at ∼ 2 nm. Dielectric constant and electrical conduction mechanisms of nc-Co:Al₂O₃ layers integrated in metal-insulator-metal capacitive structures were studied for different doping levels and for a broad temperature range (303-473 K). It was concluded that the dielectric constant in the films depends on the doping levels while the major electrical conduction mechanisms are best described by the space charge limited currents formalism, in which the current density J on an applied voltage V follow a power-law dependence (J ∼ Vⁿ) at applied voltages higher than ∼ 2 V. Such composite may find immediate applications as dielectric layers with controlled discharging conduction paths in Radio Frequency-Micro-Electro-Mechanical Systems capacitive structures.     

Ammonia-free chemically deposited CdS films as active layers in thin film transistors

In this work we have grown CdS thin films using an ammonia-free chemical bath deposition process for the active layer in thin film transistors. The CdS films were deposited substituting sodium citrate for ammonia as the complexing agent. The electrical characterization of the as-deposited CdS-based thin film transistors shows that the field effect mobility and threshold voltage were in the range of 0.12-0.16 cm²V⁻¹ s⁻¹ and 8.8-25 V, respectively, depending on the channel length. The device performance was improved considerably after thermal annealing in forming gas at 250 °C for 1 h. The mobility of the annealed devices increased to 4.8-8.8 cm²V⁻¹ s⁻¹ and the threshold voltage decreased to 8.4-12 V. I_on/I_off for the annealed devices was approximately 10⁵-10⁶.     

An investigation on palladium sulphide (PdS) thin films as a photovoltaic material

Polycrystalline PdS thin films with tetragonal structure have been grown by direct sulphuration of Pd layers. They are formed by crystallites of size ∼ 50 nm. As-grown PdS films show a Seebeck coefficient, S = − 250 ± 30 μV/K, which indicates an n-type conductivity. Electrical resistivity of the samples, measured by the four contact probe, is (6.0 ± 0.6) × 10^− 2 Ω·cm. Hall effect measurements, confirms n-type conductivity with a negative carrier density n = (8.0 ± 2.0) × 10¹⁸ cm^− 3 and electron mobility μ of (20 ± 2) cm²/V s. Band gap energy (E_g) and absorption coefficient (α) are determined from the optical transmission and reflectance of the films. A direct transition with energy gap E_g = (1.60 ± 0.01) eV is obtained. Optical absorption coefficient in the range of photon energies hν > 2.0 eV is higher than 10⁵ cm^− 1. All these properties make PdS thin films a good alternative material for solar applications.     

Electrical behavior of p-type PbS-based metal-oxide-semiconductor thin film transistors

Chemically deposited lead sulfide (PbS) thin films were used as the semiconductor active layer in common-gated thin film transistors. The PbS films were deposited at room temperature on SiO₂/Si-p wafers. Lift-off was used to define source and drain contacts (gold, Au) on top of the PbS layer with channel lengths ranging from 10 to 80 μm. The Si-p wafer with a back chromium-gold contact served as the common gate for the transistors. Experimental results show that as-deposited PbS are p-type in character and the devices exhibit typical drain current versus source-drain voltage (I_DS-V_DS) behavior as a function of gate voltage. The values of threshold voltage of the devices were in the range from −7.8 to 1.0 V, depending on the channel length. Channel mobility was approximately 10^− 4 cm²V^− 1 s^− 1. The low channel mobility in the devices is attributed to the influence of the microstructure of the nanocrystalline thin films. The electrical performance of the PbS-based devices was improved by thermal annealing the devices in forming gas at 250 °C. In particular, channel mobility increased and threshold voltage decreased as a consequence of the thermal annealing.     

Antimony sulfide thin films in chemically deposited thin film photovoltaic cells

Antimony sulfide thin films of thickness ≈ 500 nm have been deposited on glass slides from chemical baths constituted with SbCl₃ and sodium thiosulfate. Smooth specularly reflective thin films are obtained at deposition temperatures from − 3 to 10 °C. The differences in the film thickness and improvement in the crystallinity and photoconductivity upon annealing the film in nitrogen are presented. These films can be partially converted into a solid solution of the type Sb₂S_xSe_3 − x, detected in X-ray diffraction, through heating them in contact with a chemically deposited selenium thin film. This would decrease the optical band gap of the film from ≈ 1.7 eV (Sb₂S₃) to ≈ 1.3 eV for the films heated at 300 °C. Similarly, heating at 300 °C of sequentially deposited thin film layers of Sb₂S₃-Ag₂Se, the latter also from a chemical bath at 10 °C results in the formation of AgSb(S/Se)₂ with an optical gap of ≈ 1.2 eV. All these thin films have been integrated into photovoltaic structures using a CdS window layer deposited on 3 mm glass sheets with a SnO₂:F coating (TEC-15, Pilkington). Characteristics obtained in these cells under an illumination of 850 W/m² (tungsten halogen) are as follows: SnO₂:F-CdS-Sb₂S₃-Ag(paint) with open circuit voltage (V_oc) 470 mV and short circuit current density (J_sc) 0.02 mA/cm²; SnO₂:F-CdS-Sb₂S₃-CuS-Ag(paint), V_oc ≈ 460 mV and J_sc ≈ 0.4 mA/cm²; SnO₂:F-CdS-Sb₂S_xSe_3 − x-Ag(paint), V_oc ≈ 670 mV and J_sc ≈ 0.05 mA/cm²; SnO₂:F-CdS-Sb₂S₃-AgSb(S/Se)₂-Ag(paint), V_oc ≈ 450 mV and J_sc ≈ 1.4 mA/cm². We consider that the materials and the deposition techniques reported here are promising toward developing ‘all-chemically deposited solar cell technologies.’     

Local modification of NaCl thin films on Cu(111) under different bias voltages

The local modification of NaCl thin films on Cu(111) under different bias voltages is investigated using a scanning tunneling microscope (STM) at room temperature. We find that the type of modification of NaCl thin films is dependent on sample bias voltage (V_s). Defects in a triple-layer-thick NaCl film are destabilized and repelled away from the region beneath an STM tip by applying V_s in the range of 0.3 V ≤ |V_s| ≤ 0.5 V. When V_s is larger than + 1.2 V or smaller than − 4.0 V, the removal of NaCl films takes place and a bare Cu surface appears. In this case, the removed NaCl is transferred to the STM tip and can be supplied back to the surface from the STM tip. The redeposition of NaCl enables not only the reformation of single-crystalline NaCl films on a bare Cu surface but also the formation of additional NaCl films on a clean NaCl film surface.     

Electrical conduction mechanism in plasma polymerized 1-Benzyl-2-methylimidazole thin films under static electric field

The electrical properties of alternating current plasma polymerized 1-Benzyl-2-methylimidazole (PPBMI) thin films were investigated to determine the dominant carrier transport mechanism under static electric field. Fourier transform infrared (FTIR) spectroscopy was employed for structural analysis of the monomer and that of the PPBMI. The FTIR analyses demonstrate that the chemical structure of PPBMI thin films is changed to some extent from that of the monomer. Current density-voltage characteristics were studied over the temperature range from 300 to 423 K for PPBMI thin films of thicknesses 100, 150, 200 and 250 nm in Al/PPBMI/Al sandwich configuration. It is revealed that the dominant conduction mechanism in PPBMI thin films is space charge limited conduction. The activation energy for the conduction mechanism is found to be 0.43 eV. Carrier mobility, free carrier density and trap density are found to be 1.48 × 10^− 18 to 6.35 × 10^− 18 m² V^− 1 s^− 1, 1.59 × 10²³ to 5.85 × 10²³ m^− 3 and 2.50 × 10²⁴ to 5.00 × 10²³ m^− 3, respectively.     

Testing field and annealing temperature dependence of leakage properties in Bi3.25La0.75Ti3O12 thin films

Ferroelectric Bi_3.25La_0.75Ti₃O₁₂ thin films annealed at different temperatures were prepared on Pt/Ti/SiO₂/Si substrates by metalorganic decomposition method. The leakage current behavior and the current conduction mechanism were investigated. For all films, the leakage current density − electric field (J−E) characteristic is confined within a “triangle” in the log (J)− log (E) plane bounded by three limiting curves: Ohm's law (J ∝ E), trap-filled-limit (J ∝ E^a, a > 1), and Child's law (J ∝ E²). At high field region, Bi_3.25La_0.75Ti₃O₁₂ thin films with grains of rod-like show higher leakage current, while films with grains of spherical- or planar-like exhibit lower leakage current.     

Epitaxial multi-component rare earth oxide for high-K application

We studied the growth and electrical properties of single crystalline mixed (Nd_1 − xGd_x)₂O₃ (NGO) thin films and compared the results with those of the binary Gd₂O₃ and Nd₂O₃ thin films, respectively. Epitaxial ternary NGO thin films were grown on Si(100) substrates using modified solid state molecular beam epitaxy. The films were characterized physically using various techniques. The capacitance equivalent oxide thickness of a 4.5 nm NGO thin film extracted from capacitance-voltage (C-V) characteristics was 0.9 nm, which is lower than all values reported earlier for other crystalline oxides. The leakage current density and the density of interface traps were 0.3 mA/cm² at |Vg − V_FB| =  1 V and 1.4 × 10¹²/cm², respectively. These excellent electrical properties of NGO thin films demonstrate that such ternary oxides could be one of the promising candidates for gate dielectrics in the upcoming generations of complementary metal oxide semiconductor (CMOS) devices.     

Composition, structural, dielectric and DC characterization of vacuum deposited ZnSe thin films

ZnSe thin films with different thicknesses are deposited onto glass substrates under a vacuum of 4×10⁻⁵ mbar by vacuum evaporation. Rutherford backscattering spectrometry is used to identify the composition of the deposited films. The composition of the deposited films is found to be nearly stoichiometric. The X-ray diffractogram reveals a cubic structure with preferential orientation along the (1 1 1) direction and structural parameters such as crystallite size D, dislocation density δ, strain ε, and lattice parameters are calculated. It is observed that the crystallite size increases from 20.11 to 55.56 nm with increase of film thickness. In the DC conduction studies the conduction mechanism is found to follow an exponential trap distribution with density of states 3.251×10⁴⁸ J⁻¹ m⁻³. The dielectric constant is calculated as 8.11 [306 K].     

Effect of thickness of ZnO active layer on ZnO-TFT's characteristics

We have investigated the electrical characteristics of ZnO thin film transistors with respect to the thickness of ZnO active layers. The ZnO layers with the thickness of 30 nm to 150 nm were deposited on bottom gate patterned Si substrate by RF sputtering at room temperature. The low-temperature oxide served as gate dielectric. As ZnO channel layer got thicker, the leakage current at V_DS = 30 V and V_G = 0 V greatly increased from 10^− 10 A to 10^− 6 A, while the threshold voltage decreased from 15 V to 10 V. On the other hand, the field effect mobility got around 0.15 cm²/V s except for the 30-nm-thick channel. Overall, the 55-nm-thick ZnO channel layer showed the best performance.     

Annealing effect on dielectric and leakage current characteristics of Mn-doped Ba0.6Sr0.4TiO3 thin films as gate insulators for low voltage ZnO thin film transistor

We report on the dielectric properties and leakage current characteristics of 3 mol% Mn-doped Ba_0.6Sr_0.4TiO₃ (BST) thin films post-annealed up to 600 °C following room temperature deposition. The suitability of 3 mol% Mn-doped BST films as gate insulators for low voltage ZnO thin film transistors (TFTs) is investigated. The dielectric constant of 3 mol% Mn-doped BST films increased from 24 at in-situ deposition up to 260 at an annealing temperature of 600 °C due to increased crystallinity and the formation of perovskite phase. The measured leakage current density of 3 mol% Mn-doped BST films remained on the order of 5 × 10^− 9 to 10^− 8 A/cm² without further reduction as the annealing temperature increased, thereby demonstrating significant improvement in the leakage current characteristics of in-situ grown Mn-doped BST films as compared to that (5 × 10^− 4 A/cm² at 5 V) of pure BST films. All room temperature processed ZnO-TFTs using a 3 mol% Mn-doped BST gate insulator exhibited a field effect mobility of 1.0 cm²/Vs and low voltage device performance of less than 7 V.     

Electrical characterisation of stearic acid/calix[4]amine Langmuir–Blodgett thin film

Within this work we deposited 16 monolayers of stearic acid alternated with 15 monolayers of calix[4]amine to form a non-centrosymmetric Langmuir–Blodgett (LB) thin film onto an aluminized (50 nm coated) glass microscopic slide. Dielectric constant and dielectric loss for the film were determined using C-f and tan (δ-f) measurements. The value of the pyroelectric figure of merit was determined as 1.73 μC m⁻² K⁻¹. To elucidate the conduction mechanism of stearic acid/calix[4]amine LB film, DC current–voltage measurements between −4 and +4 V were carried out. The I(V) behaviour shows a symmetrical and highly non-linear behaviour. Analysis of this behaviour of the stearic acid/calix[4]amine LB film showed a conductivity value of 1.12 × 10⁻¹³ S m⁻¹ for ohmic region. The exponential part of I(V) dependence obeyed the Schottky conduction mechanism with a barrier height of 1.67 eV. This LB film structure shows a typical insulating behaviour for low voltage values and the Schottky effect becomes dominant when the voltage increases. The frequency dependence of conductivity shows a power law relationship between conductance and frequency.     

Organic field-effect transistors with thermal-cured polyacrylate gate dielectric films

Chemically and thermally stable, durable, thermal-cured polyacrylates having a hydrophobic nature, which were prepared by mixing polyacrylate having reactive sites and functional-anhydride, exhibit good insulation properties and high breakdown voltage (> 4.0 MV/cm) as a dielectric. Plastic-based organic thin-film transistors with the thermal-acryl dielectric layer showed typical current-voltage characteristics; the field-effect mobility was calculated to be 0.22 cm² V^− 1 s^− 1, while the threshold voltage was approximately − 8 V. It has been found that thin dielectric layers gave higher field-effect mobility.     

The structure and properties of SnS thin films prepared by pulse electro-deposition

SnS films were prepared onto the ITO-coated glass substrates by pulse-form electro-deposition. The potential applied to the substrates was of pulse-form and its “on” potential, V_on was − 0.75 V (vs. SCE )and “off ” potential, V_off was varied in the range of − 0.1-0.5 V. The SnS films deposited at different V_off values were characterized by XRD, EDX, SEM and optical measurements. It shows that all the films are polycrystalline orthorhombic SnS with grain sizes of 21.54-26.93 nm and lattice dimensions of a = 0.4426-0.4431 nm, b = 1.1124-1.1134 nm and c = 0.3970-0.3973 nm, though the V_off has some influence on the surface morphology of the films and Sn/S ratio. When V_off = 0.1-0.3 V, the SnS films have the best uniformity, density and adhesion, and the Sn/S ratio is close to 1/1. The direct band gap of the films was estimated to be between 1.23 and 1.33 eV with standard deviation within ± 0.03 eV, which is close to the theoretical value. The SnS films exhibit p-type or n-type conductivity and their resistivity was measured to be 16.8-43.1 Ω cm.     

Synthesis of β-FeSi2/Si heterojunctions for photovoltaic applications by unbalanced magnetron sputtering

We report here the possibility of the growth of semiconducting FeSi₂ layers on Si(100) substrates by depositing iron with unbalanced magnetron sputtering. The originality of the study is the achievement of heterojunction without any further treatment of the deposited films. Pure iron is deposited on Si(100) substrates with unbalanced magnetron sputtering for the production of β-FeSi₂/Si heterojunctions. Prior to coating process the substrates are cleaned with neutral molecular source. Microstructure of β-FeSi₂ films were investigated by X-Ray Diffraction analysis and Raman Spectroscopy. Dark current-voltage characteristic of the deposited coatings showed a rectifying behavior for the β-FeSi₂/Si heterojuctions. Open-circuit voltage (V_oc) and short-circuit current density (J_sc) were measured under 100 mWcm^− 2 illumination and a V_oc of 360 mV and J_sc of 180 μAcm^− 2 were measured. The illumination of the silicon side gave higher photosensitivity than the illumination of the iron silicide side.     

Amorphous structure and electrical performance of low-temperature annealed amorphous indium zinc oxide transparent thin film transistors

The effect of low-temperature (200 °C) annealing on the threshold voltage, carrier density, and interface defect density of amorphous indium zinc oxide (a-IZO) thin film transistors (TFTs) is reported. Transmission electron microscopy and x-ray diffraction analysis show that the amorphous structure is retained after 1 h at 200 °C. The TFTs fabricated from as-deposited IZO operate in the depletion mode with on-off ratio of > 10⁶, sub-threshold slope (S) of ~ 1.5 V/decade, field effect mobility (μ_FE) of 18 ± 1.6 cm²/Vs, and threshold voltage (V_Th) of − 3 ± 0.7 V. Low-temperature annealing at 200 °C in air improves the on-current, decreases the sub-threshold slope (1.56 vs. 1.18 V/decade), and increases the field effect mobility (μ_FE) from 18.2 to 23.3 cm²/Vs but also results in a V_Th shift of − 15 ± 1.1 V. The carrier density in the channel of the as-deposited (4.3 × 10¹⁶ /cm³) and annealed at 200 °C (8.1 × 10¹⁷ /cm³) devices were estimated from test-TFT structures using the transmission line measurement methods to find channel resistivity at zero gate voltage and the TFT structures to estimate carrier mobility.